AMD SB600 Technical Reference Manual page 189

Field Name
Reserved
Master Latency Timer
Master Latency Timer: This register specifies the value of Latency Timer in units of PCICLKs.
Field Name
Header Type
Header Type Register: This register identifies the IDE controller module as a single function device.
Field Name
Built-in-Self Test Mode
BIST Mode Type Register: This register is used for control and status for Built-in-Self test. The IDE host controller
has no BIST modes
Field Name
Resource Type Indicator
Reserved
Primary IDE CS0 Base
Address
Reserved
Base Address 0 Register (Primary CS0): This register identifies the base address of a contiguous IO space of
command register block for the primary channel.
Field Name
Resource Type Indicator
Reserved
Primary IDE CS1 Base
Address
Reserved
Base Address 1 Register (Primary CS1): This register identifies the base address of a contiguous IO space of
command register block for the primary channel.
Field Name
Resource Type Indicator
Reserved
Secondary IDE CS0
Base Address
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Master Latency Timer - RW - 8 bits - [PCI_Reg:0Dh]
Bits Default
2:0 0h They are not used and wired to 0.
7:3 00h Master Latency Timer. This number represents the guaranteed
time slice allotted to IDE host controller for burst transactions.
Header Type - R - 8 bits - [PCI_Reg:0Eh]
Bits Default
7:0 00h Header Type. Since the IDE host controller is a single-function
device, this register contains a value of 00h.
BIST Mode Type - R - 8 bits - [PCI_Reg:0Fh]
Bits Default
7:0 00h Built-in-Self Test modes. Since the IDE host controller does
not support BIST modes, this register is always read as 00.
Base Address 0 - RW - 32 bits - [PCI_Reg:10h]
Bits Default
0 1b RTE (Resource Type Indicator). This bit is wired to 1 to
indicate that the base address field in this register maps to I/O
space.
2:1 00b Reserved. Always read as 0's.
15:3 0000h
Base Address for Primary IDE Bus CS0. This
used for native mode only. Base Address 0 is not used
in compatibility mode.
31:16 0000h Reserved. Always read as 0's.
Base Address 1 - RW - 32 bits - [PCI_Reg:14h]
Bits Default
0 1b RTE (Resource Type Indicator). This bit is wired to 1 to
indicate that the base address field in this register maps to I/O
space.
1 0b Reserved. Always read as 0's.
15:2 0000h
Base Address for Primary IDE Bus CS1. This
used for native mode only. Base Address 1 is not used
in compatibility mode.
31:16 0000h Reserved. Always read as 0's.
Base Address 2 - RW - 32 bits - [PCI_Reg:18h]
Bits Default
0 1b RTE (Resource Type Indicator). This bit is wired to 1 to
indicate that the base address field in this register maps to I/O
space.
2:1 00b Reserved. Always read as 0's.
15:3 0000h
Base Address for Secondary IDE Bus CS0. This
used for native mode only. Base Address 2 is not used
in compatibility mode.
Description
Description
Description
Description
Description
Description
IDE Controller (Device 20, Function 1)
Proprietary
register is
register is
register is
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