AMD SB600 Technical Reference Manual page 18

Field Name
Minimum Grant
Field Name
Maximum Latency
Field Name
Subclass code write
Enable
Disable Dynamic Sata
Memory Power Saving
Enable dynamic Sata
Core Power Saving
Reserved
Disable Speed up XP
Boot
Reserved
Reserved
Disable port0
Disable port1
Disable port2
Disable port3
Reserved
Watch Dog Control And Status - RW - 16 bits - [PCI_Reg:44h]
Field Name
Watchdog Enable
Watchdog Timeout
Status
Reserved
Field Name
Watchdog Counter
Reserved
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Min_gnt - R - 8 bits - [PCI_Reg:3Eh]
Bits Default
7:0 00h This register specifies the desired settings for how long of a
burst the SATA controller needs. The value specifies a period
of time in units of ¼ microseconds.
Hard-wired to 0's and always read as 0's.
Max_latency - R - 8 bits - [PCI_Reg:3Fh]
Bits Default
7:0 00h This register specifies the Maximum Latency time required
before the SATA controller as a bus-master can start an
accesses
Hard-wired to 0's and always read as 0's.
Misc Control - RW - 32 bits - [PCI_Reg:40h]
Bits Default
0 0b Once set, Program Interface register (PCI_Reg:09h), subclass
code register (PCI_Reg:0Ah) and Multiple Message Capable
bits (PCI_Reg50h[19:17]) can be programmable.
1 0b When clear, dynamic power saving function for SATA internal
memory macros will be performed to reduce power
consumption.
2 0b When set, dynamic power saving function for SATA core clock
will be performed during partial/slumber mode to reduce power
consumption.
3 Reserved.
4 0b When clear, it fastens XP boot up in IDE mode. However, this
bit needs to be set, when enable SATA partial/slumber power
function is in IDE mode.
When set, the SATA partial/slumber power function can be
enabled in IDE mode, but the BIOS IO trap is needed to speed
up XP boot-up in IDE mode.
Please refer to BAR5 + offset 12C/1Ac/22C/2AC[11:8] for the
SATA partial/slumber modes that are allowed.
5 0b Reserved
15:6 Reserved.
16 0b When set, port0 is disabled and port0 clock is shut down.
17 0b When set, port1 is disabled and port1 clock is shut down.
18 0b When set, port2 is disabled and port2 clock is shut down.
19 0b When set, port3 is disabled and port3 clock is shut down.
31:20 Reserved.
Bits Default
0 0b Set this bit to enable the watchdog counter for all the PCI
down stream transaction.
1 0b Watchdog Counter Timeout Status bit. This bit indicates that
the watchdog counter has expired for PCI down stream
transaction and the transaction got aborted due to counter has
expired.
Software writes 1 to clear the status.
15:2 Reserved.
Watch Dog Counter - RW - 16 bits - [PCI_Reg:46h]
Bits Default
7:0 80h Specifies the timeout retry count for PCI down stream retries.
15:8 Reserved.
Description
Description
Description
Description
Description
SATA Registers (Device 18, Function 0)
Proprietary Page 18