AMD SB600 Technical Reference Manual page 100

Field Name
RevisionID
Class Code
Revision ID/Class Code register
Field Name
Cache Line Size
Cache line size register
Field Name
Latency Timer
Latency timer register
Field Name
Header Type
Header type register
Field Name
BIST
BIST register
Field Name
IO/Memory
Reserved
SmBusBaseAd
Base Address 0 register
Field Name
Reserved
MultiMediaTimerBaseAd
dr
Base Address 1 register
Field Name
Base Address 2
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Revision ID/Class Code- R - 32 bits - [PCI_Reg: 08h]
Bits Default
7:0 11h / This field reflects the ASIC revision.
12h / 11h : For ASIC revision A11
13h 12h : For ASIC revision A12
13h : For ASIC revision A13
For ASIC revisions after A13, by default this field will read 13h
still. However, if SMBUS PCI config 70h bit 8 is set to 1, a
hidden revision ID can be read from this field.
31:8 0C0500h 0C0500h denotes a SMBUS controller.
Cache Line Size- R - 8 bits - [PCI_Reg: 0Ch]
Bits Default
7:0 00h This register specifies the system cacheline size. This module
does not use Memory Write and Invalidate command and so
this register is not applicable. It is hardcoded to 0.
Latency Timer- R - 8 bits - [PCI_Reg: 0Dh]
Bits Default
7:0 00h This register specifies the value of the Latency Timer. This is
not used in this module and so it is always 0.
Header Type- R - 8 bits - [PCI_Reg: 0Eh]
Bits Default
7:0 80h This device is a multifunction device.
BIST- R - 8 bits - [PCI_Reg: 0Fh]
Bits Default
7:0 00h The module has no built-in self-test and so this is always 0.
Base Address 0- R - 32 bits - [PCI_Reg: 10h]
Bits Default
0 1b 1 = IO
0 = Memory
3:1 000b
31:4 0000000h SMBus Base Address
Base Address 1- R - 32 bits - [PCI_Reg: 14h]
Bits Default
9:0 000h Hardwired to 0; memory map only
31:10 000000h High Precision Event Timer (also called Multi-media Timer)
base address.
Base Address 2- R - 32 bits - [PCI_Reg: 18h]
Bits Default
31:0 0000_000 Not used and is hardcoded to 0.
0h
Description
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Description
Description
Description
Description
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Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 100