AMD SB600 Technical Reference Manual page 199

Field Name
IO Space
Memory Space
Bus Master
Special Cycles
Memory Write and
Invalidate Enable
VGA Palette Snoop
Parity Error Response
Stepping Control
SERR# Enable
Fast Back-to-Back Enable
INTA# Enable#
Reserved
Command Register: The PCI specification defines this register to control a PCI device's ability to generate and
respond to PCI cycles.
Field Name
Reserved
Interrupt A status
Capabilities List
66MHz-Capable
Reserved
Fast Back-to-Back
Capable
Master Data Parity
Error
Device Select Timing
Signaled Target Abort
Received Target Abort
Received Master Abort
Signaled System Error
Detected Parity Error
Status Register: The PCI specification defines this register to record status information for PCI related events. This
is a read/write register. However, writes can only reset bits.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
CMD- RW - 16 bits - [PCI_Reg: 04h]
Bits Default
0 0b
1 0b
2 0b
3 0b
4 0b
5 0b
6 0b
7 0b
8 0b
9 0b
10 0b
15:11 00h
STATUS- RW - 16 bits - [PCI_Reg: 06h]
Bits Default
2:0 0h
3 0b When there is interrupt A, this bit will be 1, regardless of the
value in reg0x04[10].
4 1b Read only. Indicates that the new capabilities list pointer
configuration register is implemented in reg0x34.
5 1b Read only. Indicates that device is capable of running at 66MHz.
6 0b
7 0b Read only. Indicates that device does not support fast back-to-
back transactions.
8 0b Master Data Parity Error. This bit is set to 1 when the controller
detects master data parity error. Cleared by writing a 1 to it.
10:9 10b DEVSEL# timing – Read only bits indicating DEVSEL# timing
when performing a positive decode.
11 0b Read only. The device does not support target aborts.
12 0b Received Target Abort .This bit is set to 1 when the controller,
acting as a PCI master, is aborted by a PCI target. Cleared by
writing a 1 to it.
13 0b Received Master Abort Status. Set to 1 when the controller,
acting as a PCI master, aborts a PCI bus memory cycle. Cleared
by writing a 1 to it.
14 0b SERR# status. This bit is set to 1 when the controller detects a
PCI address parity error. Cleared by writing a 1 to it.
15 0b Detected Parity Error. This bit is set to 1 when the controller
detects a parity error. Cleared by writing 1 to it.
Description
I/O Access Enable.
Memory Access Enable.
Master Enable.
Hardwired to 0 to indicate that Special Cycle recognition is
disabled.
Memory Write and Invalidate Enable.
Hardwired to 0 to indicate that the VGA Palette Snoop is
disabled. The controller does not need to snoop VGA
palette cycles.
PERR# (Response) Detection Enable bit
Hardwired to 0 to indicate that the Wait Cycle is
disenabled. The controller does not need to insert a wait
state between the address and data on the AD lines.
SERR# enable
Hardwired to 0 to indicate that Fast Back-to-back is
disabled. The controller only acts as a master to a single
device, so this functionality is not needed.
When it is 0, INTA# is allowed to send out. When it is 1,
INTA# is not allowed to send out.
Description
AC '97 Controller Functional Descriptions
Proprietary Page 199