AMD SB600 Technical Reference Manual page 132

Field Name
Dma_Page_Reserved4
Dma_Page_Reserved4 register
Field Name
Dma_PageCh6
Dma_PageCh6 register
Field Name
Dma_PageCh7
Dma_PageCh7 register
Field Name
Dma_PageCh5
Dma_PageCh5 register
Field Name
Dma_Page_Reserved5
Dma_Page_Reserved5 register
Field Name
Dma_Page_Reserved6
Dma_Page_Reserved6 register
Field Name
Dma_Page_Reserved7
Dma_Page_Reserved7 register
Field Name
Dma_Refresh
Dma_Refresh register
Field Name
FastInit
A20EnB
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Dma_Page_Reserved4- RW – 8 bits - [IO_Reg: 88h]
Bits Default
7:0 00h Dma Page Reserved4 register
Dma_PageCh6 - RW – 8 bits - [IO_Reg: 89h]
Bits Default
7:0 00h DMA2 ch 6 page register
Dma_PageCh7 - RW – 8 bits - [IO_Reg: 8Ah]
Bits Default
7:0 00h DMA2 ch 7 page register
Dma_PageCh5 - RW – 8 bits - [IO_Reg: 8Bh]
Bits Default
7:0 00h DMA2 ch 5 page register
Dma_Page_Reserved5- RW – 8 bits - [IO_Reg: 8Ch]
Bits Default
7:0 00h Dma Page Reserved5 register
Dma_Page_Reserved6- RW – 8 bits - [IO_Reg: 8Dh]
Bits Default
7:0 00h Dma Page Reserved6 register
Dma_Page_Reserved7- RW – 8 bits - [IO_Reg: 8Eh]
Bits Default
7:0 00h Dma Page Reserved7 register
Dma_Refresh- RW – 8 bits - [IO_Reg: 8Fh]
Bits Default
7:0 00h DMA2 ch4 page register.
FastInit- RW – 8 bits - [IO_Reg: 92h]
Bits Default
0 0b FAST_INIT. This read/write bit provides a fast software
executed processor reset function. Writing
a 1 to this bit will cause the INIT assertion for approximately
4ms.
Before another INIT pulse can be generated via this register,
this bit must be written back to a 0.
1 0b A20Enable Bar bit; if set to 1, A20M is disabled.
Description
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SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 132