Register Descriptions: Pci Devices; Sata Registers (Device 18, Function 0); Pci Configuration Space - AMD SB600 Technical Reference Manual

2 Register Descriptions: PCI Devices

2.1

SATA Registers (Device 18, Function 0)

Note: Some SATA functions are controlled by, and associated with, certain PCI configuration registers in the
SMBus/ACPI device. For more information refer to
0). The diagram below lists these SATA functions and the associated registers.
Function
2.1.1

PCI Configuration Space

The PCI Configuration Space registers define the operation of the SB600's SATA controller on the PCI bus.
These registers are accessible only when the SATA controller detects a Configuration Read or Write
operation, with its IDSEL asserted, on the 32-bit PCI bus.
Bus Master Interface Base Address
Subsystem ID and Subsystem Vendor ID
Power Management Control And Status
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA
SATA Enables
SATA power saving
SATA Interrupt Map register
SATA Smart Power Control
5Ch
Register Name
Vendor ID
Device ID
Command
Status
Revision ID/Class Code
Cache Link Size
Master Latency Timer
Header Type
BIST Mode Type
Base Address 0
Base Address 1
Base Address 2
Base Address 3
AHCI Base Address
Capabilities Pointer
Interrupt Line
Interrupt Pin
Min_gnt
Max_latency
Misc control
Watch Dog Control And Status
Watch Dog Counter
MSI Control
MSI Address
MSI Upper Address
MSI Data
Power Management Capability ID
Power Management Capability
section 2.3: SMBus Module and ACPI Block (Device 20,
PCI_Reg:
AC/AFh
98h
SATA Registers (Device 18, Function 0)
Proprietary
Offset Address
00h
02h
04h
06h
08h
0Ch
0Dh
0Eh
0Fh
10h
14h
18h
1Ch
20h
24h
2Ch
34h
3Ch
3Dh
3Eh
3Fh
40h
44h
46h
50h
54h
58h
5Ch
60h
62h
64h
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