AMD SB600 Technical Reference Manual page 91

Register reference manual
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USB PHY Status 0 – RW - 32 bits - [EOR_Reg: EHCI_EOR + 88h]
Field Name
Bits
PORT0_PHYStatus
7:0
PORT1_PHYStatus
15:8
PORT2_PHYStatus
23:16
PORT3_PHYStatus
31:24
Note: PORTx_PHYStatus[7:0] = { 0, RCKSEL, DUTYADJ[2:0], HSADJ[2:0] } where x=0 ~ 3
USB PHY Status 1 – RW - 32 bits - [EOR_Reg: EHCI_EOR + 8Ch]
Field Name
Bits
PORT4_PHYStatus
7:0
PORT5_PHYStatus
15:8
PORT6_PHYStatus
23:16
PORT7_PHYStatus
31:24
USB PHY Status 2 – RW - 32 bits - [EOR_Reg: EHCI_EOR + 90h]
Field Name
Bits
Reserved
15:0
PORT8_PHYStatus
23:16
PORT9_PHYStatus
31:24
UTMI Control – RW - 32 bits - [EOR_Reg: EHCI_EOR + 94h]
Field Name
Bits
VControl
6:0
VControlModeSel
7
Reserved
11:8
VLoadB
12
Port Number
16:13
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Default
00h
Read only. PHY Status of Port0
00h
Read only. PHY Status of Port1
00h
Read only. PHY Status of Port2
00h
Read only. PHY Status of Port3
Default
00h
Read only. PHY Status of Port4
00h
Read only. PHY Status of Port5
00h
Read only. PHY Status of Port6
00h
Read only. PHY Status of Port7
Default
Reserved
00h
Read only. PHY Status of Port8
00h
Read only. PHY Status of Port9
Default
0h
Control PHY setting
Group-0 (VControlModeSel=0)
VControl[6:0] = {RCKSEL, DUTYADJ[2:0], HSADJ[2:0]}
- HSADJ : HS TX current adjustment
000 : -10%
001 : -5%
100 : 0%
101 : +5%
110 : +10%
- DUTYADJ: adjust clk480 (in analog PHY) duty cycle from range 40-
60% to 60-40%.
- RCKSEL : to select the RCK fall into 50% or 57% of the eye
0 – 50% (center) of the eye
1 – 64% of the eye to increase setup time
Group-1 (VControlModeSel =1)
VControl[6:0] = {Reserved, TESTMODE[3:0] }
0b
To select PHY Vcontrol group0/1.
Reserved
1b
Update PHY control mode (active load)
0: Load the new VControl value to PHY/common block
1: Only VControlModeSel value to PHY will be updated for selecting
different PHY status group (see PHY status registers, EOR_Reg x88 ~
x90). But VControl[6:0] value inside PHY won't get affected.
0h
Select the corresponding port PHY or common block to load the
VControl bits.
0000 – Port0
0001 – Port1
0010 – Port2
......
1001 – Port9
1010 ~ 1110 : Reserved , no effect
1111 – Common block
Description
Description
Description
Description
OCHI USB 1.1 and EHCI USB 2.0 Controllers
Proprietary
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