Client Management Registers (Accessed Through C50H And C51H) - AMD SB600 Technical Reference Manual

Field Name
GpmPort register
Field Name
Reserved
FlashRomEn
Reserved
Isa_Misc register: FlashRom Enable. This only applies if the chip is strapped to have the ROM on the secondary
PCI bus.
Field Name
BiosRamIndex
BiosRamIndex register
Field Name
BiosRamData
BiosRamData register
Field Name
PM_Index
PM_Index register
Field Name
PM_Data
PM_Data register
2.3.3.1.2

Client Management Registers (Accessed through C50h and C51h)

©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
GpmPort - RW – 8 bits - [IO_Reg: C52h]
Bits Default
Isa_Misc - RW – 8 bits - [IO_Reg: C6Fh]
Bits Default
5:0 00h
6 0b Flash program enable. This only applies if the chip is
strapped to have the ROM on the PCI bus . Set to 1 to enable
programming of the Flash ROM. During write cycles to the
system ROM space, ROMCS# is only asserted if this bit is
set 1.
7 0b
BIOSRAM_Index - RW – 8 bits - [IO_Reg: CD4h]
Bits Default
7:0 00h BIOS RAM index register. This register selects one of the
256 bytes of BIOS RAM. Data in this RAM is preserved until
RSMRST# is asserted, or S5 power is lost.)
BIOSRAM_Data - RW – 8 bits - [IO_Reg: CD5h]
Bits Default
7:0 00h Power management data register. This register provides the
read/write access to the indexed register.
PM_Index - RW – 8 bits - [IO_Reg: CD6h]
Bits Default
7:0 00h Power management index register. This register selects one
of the Power Management registers. (See section
more information.)
PM_Data - RW – 8 bits - [IO_Reg: CD7h]
Bits Default
7:0 00h Power management data register. This register provides the
read/write access to the indexed register. (See section
2.3.3.2
Register Name
IdRegister
TempStatus
TempInterrupt
I2Ccontrol
Index13
Description
Description
Description
Description
Description
Description
for more information.)
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary
for
2.3.3.2
Offset Address
00h
02h
03h
12h
13h
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