AMD SB600 Technical Reference Manual page 72

Field Name
Reserved
Interrupt Status
Capabilities List
66 MHz Capable
Reserved
Fast Back-to-Back
Capable
Master Data Parity Error
DEVSEL timing
Signaled Target Abort
Received Target Abort
Received Master Abort
Signaled System Error
Detected Parity Error
Field Name
Revision ID
PI
SC
BC
Field Name
Cache Line Size
Latency Timer
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Status – R - 16 bits - [PCI_Reg : 06h]
Bits Default
2:0
3 0b
4 1b
5 1b
6
7 1b
8 0b
10:9 01b
11 0b
12 0b
13 0b
14 0b
15 0b
Revision ID / Class Code – R - 32 bits - [PCI_Reg : 08h]
Bits Default
7:0 00h
15:8 20h
23:16 03h
31:24 0Ch
Miscellaneous – RW - 32 bits - [PCI_Reg : 0Ch]
Bits Default
7:0 00h
15:8 00h
Description
Reserved
This bit reflects the state of the interrupt in the
device/function. Only when the Interrupt Disable bit in the
command register is a 0 and this Interrupt Status bit is a 1,
will the device's/function's INTx# signal be asserted. Setting
the Interrupt Disable bit to a 1 has no effect on the state of
this bit.
A value of 0 indicates that no New Capabilities linked list is
available.
A value of 1 indicates that the value read at offset 34h is a
pointer in Configuration Space to a linked list of new
capabilities.
Hard-wired to 1, indicating 66MHz capable.
Reserved
Hard-wired to 1, indicating Fast Back-to-Back capable.
This bit is set only when three conditions are met: 1) the bus
agent asserted PERR# itself (on a read) or observed PERR#
asserted (on a write); 2) the agent setting the bit acted as the
bus master for the operation in which the error occurred; and
3) the Parity Error Response bit (Command register) is set.
Hard-wired to 01b – medium timing
This bit is set by a target device whenever it terminates a
transaction with Target-Abort.
This bit is set by a master device whenever its transaction is
terminated with Target-Abort.
This bit is set by a master device whenever its transaction
(except for Special Cycle) is terminated with Master-Abort.
This bit is set whenever the device asserts SERR#.
This bit is set by the device whenever it detects a parity error,
even if parity error handling is disabled (as controlled by bit 6
in the Command register).
Description
Revision ID.
Programming Interface. A constant value of '20h' indentifies
the device being an EHCI Host Controller.
Sub Class. A constant value of '03h' indentifies the device
being of Universal Serial Bus.
Base Class. A constant value of '0Ch' identifies the device
being a Serial Bus Controller.
Description
This read/write field specifies the system cacheline size in
units of DWORDs and must be initialized to 00h.
[9:8] hard-wired to 00b, resulting in a timer granularity of at
least four clocks. This field specifies, in units of PCI bus
clocks, the value of the Latency Timer for this PCI bus
master.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
Proprietary Page 72