AMD SB600 Technical Reference Manual page 192

IDE Legacy DMA (Multi-words DMA) Timing Modes - RW - 32 bits - [PCI_Reg:44h]
Field Name
IDE Legacy DMA (Multi-words DMA) Timing Modes Register: This register controls the IDE interface and selects
the timing of the IDE DMA bus-master cycles.
Note: Relation of setting value and actual timing of each mode are
DMA Mode 2
Command Width 2(90ns) 2(90ns) 7(240ns)
Recover Width 0(30ns) 1(60ns) 7(240ns)
The above timings are valid and A-Link clock is always 66MHz.
Actual timing is setting value + 1 A-Link clock cycle.
Field Name
Primary IDE Disable
Reserved
Reserved
Reserved
Reserved
IDE PIO Control Register: This register controls the IDE interface and selects the control functions of the PCI bus
IDE PIO bus-master cycles.
Field Name
Primary Master PIO
Access Mode
Reserved
Primary Slave PIO
Access Mode
Reserved
IDE PIO Mode Register: This register specifies PIO modes primary channel.
Field Name
Reserved
IDE Status Register: This register specifies the IDE Status of primary channel.
Field Name
Primary Master Ultra
DMA enable
Primary Slave Ultra DMA
enable
Reserved
Ultra DMA Report Mode
IDE Ultra DMA Control Register: This register specifies the IDE Control of primary channel.
Field Name
Primary Extra Data
Status
Reserved
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Bits Default
1 0
IDE PIO Control - RW - 16 bits - [PCI_Reg:48h]
Bits Default
0 0b Disable Primary IDE controller. When set Primary IDE
controller is disabled.
3:1 000b Reserved. Always read as 0's
8:4 00h Obsolete bits
11:9 000b Reserved. Always read as 0's
15:12 0h Obsolete bits
IDE PIO Mode - RW- 16 bits - [PCI_Reg:4Ah]
Bits Default
2:0 0h PIO access mode for Primary IDE Master device. For
instance, PIO 0 = 000, PIO 1 = 001, ... etc..
3 0b Reserved. Always read as 0's.
6:4 0h PIO access mode for Primary IDE Slave device. For instance,
PIO 0 = 000, PIO 1 = 001, ... etc..
15:7 000h Reserved. Always read as 0's.
IDE Status - R- 8 bits - [PCI_Reg:4Ch]
Bits Default
7:0 00h Reserved. These bits always read as0's.
IDE Ultra DMAControl - RW- 8 bits - [PCI_Reg:54h]
Bits Default
0 0b Ultra DMA Enable Primary IDE Master device.
1 0b Ultra DMA Enable Primary IDE Slave device.
6:2 00000b Reserved. Always read as 0's.
7 0b Report Mode.
When host receives last data as extra word, reporting will be:
If this bit is 1, set IDE Ultra DMA Status register only.
If this bit is 0, clear the interrupt bit of BusMaster Status
Register and also set IDE Ultra DMA Status Register.
IDE Ultra DMA Status - RW- 8 bits - [PCI_Reg:55h]
Bits Default
0 0b Transaction is complete, but internal buffer has some data.
This bit will be cleared by resetting the DMA start bit.
7:1 00h Reserved. Always read as 0's.
Description
Description
Description
Description
Description
Description
IDE Controller (Device 20, Function 1)
Proprietary Page 192