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Field Name
ExtEvent0Status
ExtEvent1Status
PCIePmeStatus
GPM0Status
GPM1Status
GPM2Status
GPM3Status
GPM8Status
SmiSciSts2 register
Field Name
Gpio0Status
GPM4Status
GPM5Status
AzaliaStatus
GPM6Status
GPM7Status
Gpio2Status
SataSciStatus
SmiSciSts3 register
Field Name
Mwait_any_smi_en
Mwait_2cpu_smi_en
Mwait_4cpu_smi_en
Mwait_2cpu_C23_en
Mwait_4cpu_C23_en
Reserved
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SmiSciSts2 - RW – 8 bits - [PM_Reg: 5Ch]
Bits
Default
0
0b
This bit indicates the SMI# status of ExtEvent0 to
SCI/Wakeup if it is configured to generate SMI# followed by
SCI
1
0b
This bit indicates the SMI# status of ExtEvent1 to
SCI/Wakeup if it is configured to generate SMI# followed by
SCI
2
0b
This bit indicates the SMI# status of the PME# from
PCIExpress if it is configured to generate SMI# followed by
SCI
3
0b
This bit indicates the SMI# status of GPM[0] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
4
0b
This bit indicates the SMI# status of GPM[1] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
5
0b
This bit indicates the SMI# status of GPM[2] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
6
0b
This bit indicates the SMI# status of GPM[3] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
7
0b
This bit indicates the SMI# status of GPM[8] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
SmiSciSts3 - RW – 8 bits - [PM_Reg: 5Dh]
Bits
Default
0
0b
This bit indicates the SMI# status of GPIO0 (or
WAKE#/GEVENT8 pin if PM IO Reg 84h bit1 =1) to
SCI/wakeup if it is configured to generate SMI# followed by
SCI
1
0b
This bit indicates the SMI# status of GPM[4] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
2
0b
This bit indicates the SMI# status of GPM[5] to SCI/Wakeup
3
0b
This bit indicates the SMI# status from the internal HD Audio
controller if it is configured to generate SMI# followed by SCI
4
0b
This bit indicates the SMI# status of GPM[6] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
5
0b
This bit indicates the SMI# status of GPM[7] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
6
0b
This bit indicates the SMI# status of GPIO2 to SCI/wakeup if
it is configured to generate SMI# followed by SCI
7
0b
This bit indicates the SMI# status of SataSci to SCI/wakeup
MwaitEnable - RW – 8 bits - [PM_Reg: 5Eh]
Bits
Default
0
0b
SMI# is generated when any CPU is in mwait state if this bit
is set to 1
1
0b
For 2 CPU system (dual core, non HT) SMI# is generated
when both CPUs are in mwait state if this bit is set to 1
2
0b
For 4 CPU system (dual core, HT) SMI# is generated when
all 4 CPUs are in mwait state if this bit is set to 1
3
0b
For 2 CPU system (dual core, non HT) C2 or C3 is generated
when both CPUs are in mwait state if this bit is set to 1. C2 or
C3 is determined by ARB_DIS = 0 or 1.
4
0b
For 4 CPU system (dual core, HT) C2 or C3 is generated
when all 4 CPUs are in mwait state if this bit is set to 1. C2 or
C3 is determined by ARB_DIS = 0 or 1.
7:5
000b
Description
Description
Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary
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