AMD SB600 Technical Reference Manual page 230

Field Name
Interrupt Line
Interrupt Pin
Reserved
Field Name
Minimum Grant
Field Name
Maximum Latency
Field Name
Disable Non-noop
Disable Non-snoop
Override
Enable Non-snoop
Request
Reserved
Interrupt Pin Control Register – RW – 8 bits – [PCI_Reg: 44h]
Field Name
Interrupt Pin Control
Reserved
Power Management Capability ID – R – 16 bits – [PCI_Reg: 50h]
Field Name
Capability ID
Next Capability Pointer
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Interrupt Line – RW – 8 bits – [PCI_Reg: 3Ch]
Bits Default
7:0 00h
Interrupt Pin – R – 8 bits – [PCI_Reg: 3Dh]
3:0 1h
7:4 0h
Minimum Grant – R – 8 bits – [PCI_Reg: 3Eh]
Bits Default
7:0 00h
Maximum Latency – R – 8 bits – [PCI_Reg: 3Fh]
Bits Default
7:0 00h
Misc Control Register – RW – 8 bits – [PCI_Reg: 42h]
Bits Default
0 0b
1 0b
2 0b
7:3 00h
Bits Default
3:0 1h
7:4 0h
Bits Default
7:0 01h
15:8 60h
Description
This register is used to communicate to software the
interrupt line that the interrupt pin is connected to. It is not
used by the HD Audio controller.
This register reflects the value programs into Interrupt
Control Pin register at offset 44h, bits[3:0]
Reserved
Description
Hardwired to "0".
Description
Hardwired to "0".
Description
1: Non-snoop attribute is disabled on Buffer Descriptor and
Data Buffer DMA.
0: Set the Non-snoop attribute on Buffer Descriptor and
Data Buffer DMA when the Traffic Priority bit is set in the
Stream Descriptor.
1: Bit[0] of this register controls the Non-snoop attribute
0: override the bit[0] setting meaning always generate No
Snoop attribute on Buffer Descriptor and Data Buffer DMA
1: Enable Non-snoop request to ACPI
0: Disable Non-snoop request to ACPI
When enabled and the DMA cycle is Non-snoop, ACPI will
not generate a wake to CPU in C2 state.
Reserved
Description
Controls the value reports in Interrupt Pin Register at offset
0x3D.
Reserved
Description
Hardwired to 01h. Indicates PCI Power Management
Capability.
Hardwired to 60h.
Next capability is at offset 60h
Proprietary
HD Audio Controllers Registers
Page 230