Gpm Pins As Output; Extevent; Extevent As Gpio; Extevent To Generate Smi - AMD SB600 Technical Reference Manual

4.2.3.2

GPM pins as Output

For GPM[7:0], follow this sequence -
1. Set index register 0C50h to 13h (Misc. Control).
2. Set CM Data register 0C51h Bits [7:6] = 01b to set Input/Out control.
3. Set GPM port 0C52h appropriate bits to 0 to enable output on the GPM port.
4. Set CM Data register 0C51h Bits [7:6] = 10b for output data control.
5. Write the output data to port 0C52h.
For GPM[9:8], simply use PM I/O 95h Bits [1:0] as output enable (0: enable; 1: tri-state) and 94h Bits [1:0] as
output value (0: output low; 1: output high).
4.2.4

ExtEvent

4.2.4.1

ExtEvent as GPIO

Table 4-4: ExtEvent Pins as GPIO

Pin Name Output Enable
EXTEVNT0#/ PM IO Reg91h[Bit 0]
RI# 0: Output enable
1: Input (Tri-state)
EXTEVNT1#/ PM IO Reg91h[Bit 1]
LPC_SMI# 0: Output enable
1: Input(Tri-state)
4.2.4.2

ExtEvent to Generate SMI#

EXTEVNT[1:0] can generate SCI or SMI#/SMI#/SMI# followed by SCI/IRQ13 as described in section 4.2.2.
These pins can also be programmed to generate SMI# by the following alternate method.

Table 4-5: ExtEvent Pins to Generate SMI#

Pin Name* Trigger
1 – Rising edge
0 – Falling edge
EXTEVNT0#/ PM IO
RI# Reg0Dh[Bit 2]
EXTEVNT1#/ PM IO
LPC_SMI# Reg0Dh[Bit 3]
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Output Register
PM IO Reg90h[Bit 0]
0: Output low
1: Output high
PM IO Reg90h[Bit 1]
0: Output low
1: Output high
Enable SMI# SMI# Status
PM IO PM IO
Reg04h[Bit 0] Reg07h[Bit 0]
PM IO PM IO
Reg04h[Bit 1] Reg07h[Bit 1]
Input Status
PM IO Reg0Dh[Bit 0]
PM IO Reg0Dh[Bit 1]
Logical Value
Read only
PM IO
Reg0Dh[Bit 0]
PM IO
Reg0Dh[Bit 1]
GEVENT/GPE/GPM/ExtEvent
Proprietary
Power Domain
S5
S0
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