AMD SB600 Technical Reference Manual page 233

Immediate Command Input Interface
Immediate Command Input Interface
DMA Position Buffer Lower Base Address
DMA Position Buffer Upper Base Address
Buffer Descriptor Lower Base Address
Buffer Descriptor Upper Base Address
Buffer Descriptor Lower Base Address
Buffer Descriptor Upper Base Address
Buffer Descriptor Lower Base Address
Buffer Descriptor Upper Base Address
Buffer Descriptor Lower Base Address
Buffer Descriptor Upper Base Address
Buffer Descriptor Lower Base Address
Buffer Descriptor Upper Base Address
Buffer Descriptor Lower Base Address
Buffer Descriptor Upper Base Address
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Register Name
Control
Status
Link Position in Current Buffer
Cyclic Buffer Length
Last Valid Index
FIFO Size
Stream Format
Control
Status
Link Position in Current Buffer
Cyclic Buffer Length
Last Valid Index
FIFO Size
Stream Format
Control
Status
Link Position in Current Buffer
Cyclic Buffer Length
Last Valid Index
FIFO Size
Stream Format
Control
Status
Link Position in Current Buffer
Cyclic Buffer Length
Last Valid Index
FIFO Size
Stream Format
Control
Status
Link Position in Current Buffer
Cyclic Buffer Length
Last Valid Index
FIFO Size
Stream Format
Control
Status
Link Position in Current Buffer
Cyclic Buffer Length
Last Valid Index
FIFO Size
Stream Format
Address Offset
HD Audio Controllers Registers
Proprietary
64h
68h
70h
74h
80h
83h
84h
88h
8Ch
90h
92h
98h
9Ch
A0h
A3h
A4h
A8h
ACh
B0h
B2h
B8h
BCh
C0h
C3h
C4h
C8h
CCh
D0h
D2h
D8h
DCh
E0h
E3h
E4h
E8h
ECh
F0h
F2h
F8h
FCh
100h
103h
104h
108h
10Ch
110h
112h
118h
11Ch
120h
123h
124h
128h
12Ch
130h
132h
138h
13Ch
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