AMD SB600 Technical Reference Manual page 78

Field Name
Bar #
Field Name
Capability ID
Next EHCI Extended
Capability Pointer
HC BIOS Owned
Semaphore
Reserved
HC OS Owned Semaphore
Reserved
USBLEGCTLSTS – RW - 32 bits - [PCI_Reg : EECP + 04h]
Field Name
USB SMI Enable
SMI on USB Error Enable
SMI on Port Change
Enable
SMI on Frame List Rollover
Enable  R /W
SMI on Host System Error
Enable
SMI on Async Advance
Enable
Reserved.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
DBUG_PRT Control – R - 32 bits - [PCI_Reg : E4h]
Bits Default
31:29 1h
USBLEGSUP – RW - 32 bits - [PCI_Reg : EECP + 00h]
Bits Default
7:0 01h
15:8 00h
16 0b
23:17
24 0b
31:25
Bits Default
0 0b
1 0b
2 0b
3 0b
4 0b
5 0b
12:6
Description
A 3-bit field, which indicates which one of the possible 6
Base Address Register offsets, contains the Debug Port
registers. For example, a value of 1h indicates the first BAR
(offset 10h) while a value of 5 indicates that the BAR at 20h.
This offset is independent as to whether the BAR is 32 or 64
bit. For example, if the offset were 3 indicating that the BAR
at offset 18h contains the Debug Port. BARs at offset 10 and
14h may or may not be implemented. This field is read only
and only values 1-6h are valid. (A 64-bit BAR is allowed.)
Only a memory BAR is allowed.
Description
This field identifies the extended capability. A value of 01h
identifies the capability as Legacy Support. This extended
capability requires one additional 32-bit register for
control/status information, and this register is located at
offset EECP+04h.
Read Only.
This field points to the PCI configuration space offset of the
next extended capability pointer. A value of 00h indicates
the end of the extended capability list.
Read Only.
The BIOS sets this bit to establish ownership of the EHCI
controller. System BIOS will set this bit to a zero in
response to a request for ownership of the EHCI controller
by system software.
These bits are reserved and must be set to zero.
System software sets this bit to request ownership of the
EHCI controller. Ownership is obtained when this bit reads
as one and the HC BIOS Owned Semaphore bit reads as 0.
These bits are reserved and must be set to zero.
Description
When this bit is a one, and the SMI on USB Complete bit
(above) in this register is a one, the host controller will issue
an SMI immediately.
When this bit is a one, and the SMI on USB Error bit (above)
in this register is a one, the host controller will issue an SMI
immediately.
When this bit is a one, and the SMI on Port Change Detect
bit (above) in this register is a one, the host controller will
issue an SMI immediately.
When this bit is a one, and the SMI on Frame List Rollover
bit (above) in this register is a one, the host controller will
issue an SMI immediately.
When this bit is a one, and the SMI on Host System Error bit
(above) in this register is a one, the host controller will issue
an SMI immediately.
When this bit is a one, and the SMI on Async Advance bit
(above) in this register is a one, the host controller will issue
an SMI immediately.
These bits are reserved and must be set to zero.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
Proprietary Page 78