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2.5.2.2
Modem Memory Mapped Registers
All the AC'97 Controller modem registers are mapped to memory.
Field Name
in DMA Overflow
in DMA Status
out DMA1 Underflow
out DMA1 Status
out DMA2 Underflow
out DMA2 Status
out DMA3 Underflow
out DMA3 Status
Phy Data Incoming
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Register Name
Interrupt
Interrupt Enable
Modem Command
Output Phy Status And Address
Input Phy Address & Data
SLOTREQ
Counter
Input Fifo Threshold
Input DMA Link List Pointer
Input DMA DT Start
Input DMA DT Next
Input DMA DT Current
Input DT Size And FIFO Info
Out Fifo's Threshold
Output DMA1 Link List Pointer
Output DMA2 Link List Pointer
Output DMA3 Link List Pointer
Output DMA1 DT Start
Output DMA1 DT Next
Output DMA1 DT Current
Output DMA2 DT Start
Output DMA2 DT Next
Output DMA2 DT Current
Output DMA3 DT Start
Output DMA3 DT Next
Output DMA3 DT Current
Output DMA 1/2 Size
Output DMA 3 DT Size
Output Dma 1/2/3 Fifo Info
Output GPIO Out Data
Input GPIO Data
Modem Mirror
Audio Mirror
Modem FIFO Flush
Phy Semphore Register
Interrupt - RW - 32 bits - [MEM_Reg: 00h]
Bits
Default
0
0b
1
0b
2
0b
3
0b
4
0b
5
0b
6
0b
7
0b
8
0b
Description
Input Channel overflow - out of FIFO space
Input Channel status bit - set to "1" after finishing DT
(if reg0x04[1]=1 and reg0x08[5]=1)
Output DMA1 underflow - no data in FIFO
Output DMA1 status bit - set to "1" after finishing DT (if
reg0x04[1]=1 and reg0x08[5]=1)
Output DMA2 underflow - no data in FIFO
Output DMA2 status bit - set to "1" after finishing DT (if
reg0x04[1]=1 and reg0x08[5]=1)
Output DMA3 underflow - no data in FIFO
Output DMA3 status bit - set to "1" after finishing DT (if
reg0x04[1]=1 and reg0x08[5]=1)
Got OR'ed Phy register address and data from Codecs
AC '97 Controller Functional Descriptions
Proprietary
Offset Address
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
4Ch
50h
54h
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
7Ch
80h
88h
A8h
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