AMD SB600 Technical Reference Manual page 165

Field Name
S0S3ToS5Enable0 register
Field Name
S0S3ToS5Enable1
S0S3ToS5Enable1 register
Field Name
S0S3ToS5Enable2
S0S3ToS5Enable2 register
Field Name
S0S3ToS5Enable3
S0S3ToS5Enable3 register
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
S0S3ToS5Enable0 – RW – 8 bits – [PM_Reg:76h]
Bits Default
S0S3ToS5Enable1 – RW – 8 bits – [PM_Reg:77h]
Bits Default
7:0 FFh This register determines which wakeup signals can be passed
onto the S5 region. For S4/S5 wake up, this bit must be set in
before the corresponding pin can be used
Bit [7:0]: GPM#[7:0]
1: Enable
0: Disable
S0S3ToS5Enable2 – RW – 8 bits – [PM_Reg:78h]
Bits Default
7:0 FFh This register determines which wakeup signals can be passed
onto the S5 region. For S4/S5 wake up, this bit must be set in
before the corresponding pin can be used
Bit [0]: Spare
Bit [1]: Internal USB
Bit [2]: EXTEVENT#[0]
Bit [3]: EXTEVENT#[1]
Bit [4]: External IRQ8
Bit [5]: GPIO[0]
Bit [6]: GPIO[1]
Bit [7]: GPIO[2]
1: Enable
0: Disable
S0S3ToS5Enable3 – RW – 8 bits – [PM_Reg:79h]
Bits Default
7:0 FFh This register determines which wakeup signals can be passed
onto the S5 region. For S4/S5 wake up, this bit must be set in
before the corresponding pin can be used
Bit [0]: GPIO[3]
Bit [1]: Spare
Bit [2]: SATA_SCI
Bit [3]: Spare
Bit [4]: Spare
Bit [5]: Spare
Bit [6]: S5ResetOverride
Bit [7]: Enable bit to pass PCI config gevent1_en* bits
1: Enable
0: Disable
Description
Description
Description
Description
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary Page 165