Display Output Registers - AMD M56 Reference Manual

2.9

Display Output Registers

Field Name
DACA_ENABLE
Turn on/off DACA
Field Name
DACA_SOURCE_SELECT
Select between 1st display, 2nd display & TV encoder streams
Field Name
DACA_CRC_EN
DACA_CRC_CONT_EN
DACA CRC enable signals
Field Name
DACA_CRC_FIELD
DACA_CRC_ONLY_BLANKb
DACA CRC controls signals
Field Name
DACA_CRC_SIG_BLUE_MASK
DACA_CRC_SIG_GREEN_MASK
DACA_CRC_SIG_RED_MASK
Mask bits for R, G & B CRC calculations
© 2007 Advanced Micro Devices, Inc.
Proprietary
DACA_ENABLE - RW - 32 bits - DISPDEC:0x7800
Bits
0
DACA_SOURCE_SELECT - RW - 32 bits - DISPDEC:0x7804
Bits
1:0
DACA_CRC_EN - RW - 32 bits - DISPDEC:0x7808
Bits
0
16
DACA_CRC_CONTROL - RW - 32 bits - DISPDEC:0x780C
Bits
0
8
DACA_CRC_SIG_RGB_MASK - RW - 32 bits - DISPDEC:0x7810
Bits
9:0
19:10
29:20
Default
0x0 0=Disable
1=Enable
Default
0x0 0=Source is CRTC1
1=Source is CRTC2
2=Source is TV Encoder
3=Reserved
Default
0x0 Enable signal for DACA CRC
0=Disable
1=Enable
0x0 Determines whether CRC is calculated continuously or for one frame
(one shot)
0=CRC is calculated over 1 frame
1=CRC is continuously calculated for every frame
Default
0x0 Controls which field polarity starts the DACA CRC block after
DACA_CRC_EN is set high. Used only for interlaced mode CRCs
0=Even field begins CRC calculation
1=Odd field begins CRC calculation
0x0 Determines whether CRC is calculated for the whole frame or only
during non-blank period for DACA
0=CRC calculated over entire field
1=CRC calculated only during BLANKb
Default
0x3ff Mask bits for DACA B channel CRC
0x3ff Mask bits for DACA G channel CRC
0x3ff Mask bits for DACA R channel CRC
Display Output Registers
Description
Description
Description
Description
Description
M56 Register Reference Manual
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