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6.2
Power Management for the Graphics Controller
The RS780E supports power management for the embedded graphics device as specified by the PCI Bus Power
Management Interface Specification version 1.0, according to which the integrated graphics core of the RS780E qualifies
as a device embedding a single function in the power management system.
6.2.1
PCI Function Power States
There are up to four power states defined for each PCI function associated with each PCI device in the system. These
power states are D0, D1, D2 and D3. D0 (on) consumes the most power while D3 (off) consumes the least. D1 and D2
enable levels of power savings in between those of D0 and D3. The concepts of these power states are universal for all
functions in the system. When transitioned to a given power management state, the intended functional behavior is
dependent upon the type (or class) of the function.
6.2.2
PCI Power Management Interface
The four basic power management operations are:
•
Capabilities Reporting
•
Power Status Reporting
•
Setting Power State
•
System Wakeup
All four of these capabilities are required for each power management function with the exception of wakeup event
generation.
This section describes the format of the registers in the PCI Configuration Space that are used by these power
management operations. The Status and Capabilities Pointer (CAP_PTR) fields have been highlighted to indicate where
the PCI Power Management features appear in the standard Configuration Space Header.
Table 6-3 Standard PCI Configuration Space Header Type 0
MSB
Device ID
Status (with Bit 4 set to 1)
Class Code
BIST
Base Address Registers
CardBus CIS Pointer
Subsystem ID
Expansion ROM Base Address
Reserved
Reserved
Max_Lat
6.2.3
Capabilities List Data Structure in PCI Configuration Space
The Capabilities bit in the PCI Status register (offset = 06h) indicates whether or not the subject function implements a
linked list of extended capabilities. Specifically, if bit 4 is set, the CAP_PTR register is implemented to give offset to the
first item in the Capabilities link list.
45732 AMD 780E Databook 3.10
6-2
Register Fields (32 Bits)
Vendor ID
Command
Revision ID
Header Type
Latency Timer
Subsystem Vendor ID
Min_Gnt
Interrupt Pin
Power Management for the Graphics Controller
LSB
00h (LSB)
04h
08h
Cache Line Size
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
CAP_PTR
34h
38h
Interrupt Line
3Ch
© 2009 Advanced Micro Devices, Inc.
Offset
Proprietary
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