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AMD SP5100 Databook
Note: LPCCLK[1:0] can be assigned to any LPC device. LPCCLK0 will be active during S2 – S5 states if the IMC is
enabled. LPCCLK1 will be disabled in S2 to S5 states. PCI Clock can be used for additional LPC devices that do not
require clock in S2 –S5 states.
7.3
A-Link Express II Interface
Pin Name
Type
PCIE_TX[3:0]P
PCIE_TX[3:0]N
PCIE_RX[3:0]P
PCIE_RX[3:0]N
PCIE_RCLKP
PCIE_RCLKN
PCIE_CALRP
PCIE_CALRN
7.4
PCI Interface (PCI Host Bus and Internal PCI/PCI Bridge)
Pin Name
Type
AD[31:0]
BMREQ#/REQ5#/
GPIO65
CBE[3:0]#
CLKRUN#
DEVSEL#
FRAME#
GNT#[2:0]
GNT3#/GPIO72
GNT4#/GPIO73
INT[H:E]#/GPIO[36:33]
IRDY#
LDRQ1#/GNT5#/
GPIO68
LOCK#
PAR
PCICLK[4:0]
PCICLK5/GPIO41
34
Voltage
O
O
I
I
I/O
1.2 V (Filtered)
I/O
O
O
Voltage
I/O
3.3 V (5-V Tolerance) PCI Bus Address/Data [31:0]
I/O
3.3 V (5-V Tolerance) Bus master REQ# / PCI Request 5 Input / GPIO 65
I/O
3.3 V (5-V Tolerance) Command/Byte Enable[3:0]
I/O
3.3 V (5-V Tolerance)
I/O
3.3 V (5-V Tolerance)
I/O
3.3 V (5-V Tolerance)
O
3.3 V (5-V Tolerance)
O
3.3 V (5-V Tolerance) PCI Bus Grant 3 from SP5100 / GPIO 72
I/O
3.3 V (5-V Tolerance) PCI Bus Grant 4 from SP5100 / GPIO 73
I/O
3.3 V (5-V Tolerance) PCI Interrupt [H:E] / GPIO [36:33]
I/O
3.3 V (5-V Tolerance)
I/O
3.3 V (5-V Tolerance)
I/OD
3.3 V (5-V Tolerance) PCI Bus Lock
I/O
3.3 V (5-V Tolerance) PCI Bus Parity
O
3.3 V (5-V Tolerance) 33-MHz PCI clocks [4:0]
3.3 V (5-V Tolerance) 33-MHz PCI clock 5 / LPC CLK 0
O
Signal Description
Functional Description
A-Link Express II Lane 3-0 Transmit Positive
A-Link Express II Lane 3-0 Transmit Negative
A-Link Express II Lane 3-0 Receive Positive
A-Link Express II Lane 3-0 Receive Negative
A-Link Express II Reference Clock Positive
A-Link Express II Reference Clock Negative
A-Link Express II Calibration, TX termination reference
resistor connection
A-Link Express II Calibration, RX termination reference
resistor connection
Functional Description
Clock running is de-asserted by the clock provider to
indicate the system is about to shut down the PCI clock.
When it is driven low by other agents, it means the agent
is requesting the clock provider not to deactivate the clock.
Device Select
Device Select: driven by target to indicate it has decoded
its address as the target of the current access.
Cycle Frame: driven by the current master to indicate the
beginning and duration of an access.
PCI Bus Grant [2:0] from the SP5100: indicates to the
agent that access to the bus has been granted.
Initiator Ready: indicates the initiating agent's ability to
complete the current data phase of the transaction
Encoded DMA/Bus Master Request 1 / PCI bus Grant 5
from SP5100 /GPIO 68
44409 Rev. 1.70 October 10
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