Display Look Up Table Control Registers - AMD M56 Reference Manual

Display Controller Registers

2.7.10 Display Look Up Table Control Registers

Field Name
DC_LUT_RW_SELECT
LUT host Read/write selection.
Field Name
DC_LUT_RW_MODE
LUT host read/write mode.
Field Name
DC_LUT_RW_INDEX
LUT index for host read/write.
Field Name
DC_LUT_SEQ_COLOR
Sequential 10-bit R,G,B host read/write for LUT 256-entry table mode.
Field Name
DC_LUT_BASE
DC_LUT_DELTA
M56 Register Reference Manual
2-226
DC_LUT_RW_SELECT - RW - 32 bits - DISPDEC:0x6480
Bits Default
0 0x0
DC_LUT_RW_MODE - RW - 32 bits - DISPDEC:0x6484
Bits Default
0 0x0
DC_LUT_RW_INDEX - RW - 32 bits - DISPDEC:0x6488
Bits Default
7:0 0x0
DC_LUT_SEQ_COLOR - RW - 32 bits - DISPDEC:0x648C
Bits Default
15:0 0x0
DC_LUT_PWL_DATA - RW - 32 bits - DISPDEC:0x6490
Bits Default
15:0 0x0
31:16 0x0
Description
LUT host Read/write selection.
0=Host reads/writes to the LUT access the lower half of the LUT
1=Host reads/writes to the LUT access the upper half of the LUT
Description
LUT host read/write mode.
0=Host reads/writes to the LUT in 256-entry table mode
1=Host reads/writes to the LUT in piece wise linear (PWL) mode
Description
LUT index for host read/write.
In 256-entry table mode: LUT_ADDR[6:0] = INDEX[7:1]. INDEX[0] is
used to select LUT lower or upper 10 bits.
In piece wise linear (PWL) mode: LUT_ADDR[6:0] = INDEX[6:0].
INDEX[7] is not used
Description
Sequential 10-bit R,G,B host read/write for LUT 256-entry table
mode. After reset or writing DC_LUT_RW_INDEX register, first
DC_LUT_SEQ_COLOR access is for red component, the second
one is for green component and the third one is for blue component.
Always access this register three times for one LUT entry in LUT
256-entry table mode. The LUT index is increased by 1 when LUT
blue data is accessed. This allow you to access the next LUT entry
without programming DC_LUT_RW_INDEX again.
NOTE: Bits 0:5 of this field are hardwired to ZERO.
Description
Linear interpolation of base value for host read/write.
NOTE: Bits 0:5 of this field are hardwired to ZERO.
Linear interpolation of delta value for host read/write. The LUT index
is increased by 1 when register DC_LUT_PWL_DATA is accessed.
NOTE: Bits 0:5 of this field are hardwired to ZERO.
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