Figure 13.3A Block Diagram Of P30/Adst Pin; Structure Of A/D Converter - Fujitsu F2MC-8L MB89620 Series Hardware Manual

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13.

Structure of A/D Converter

This section describes the pins, pin block diagrams, registers, and an interrupt source
for the A/D converter.
n A/D Converter Pins
The A/D converter uses the P30/ADST and P50/AN0 to P57/AN7 pins.
l P30/ADST pin (Also serves as the CLKO pin on products with the clock monitor function)
The P30/ADST pin can function as either a general-purpose I/O port (P30) or as an external
clock input used to activate the A/D conversion or sense function (ADST). The pin functions as
the ADST pin when the pin is set as an input port (DDR3: bit 0 = "0"), continuous activation is
enabled (ADC2: EXT = "1"), and the input clock selection bit is set to external clock input
(ADC2: ADCK = "1").
ADST: When performing continuous activation synchronized with an external clock input,
Check: The pin cannot be used as the external clock input pin (ADST) when using the pin as the clock
Figure 13.3a shows the block diagram of the P30/ADST pin.
SPL: Pin state specification bit in the standby control register (STBC).
Note: Pins with a pull-up resistor (optional) go to the "H" level during a reset or in stop mode (SPL = "1").
P50/AN0 to P57/AN7 pins
l
The P50/AN0 to P57/AN7 pins can function either as N-ch open-drain output-only ports (P50 to
P57) or as an analog input (AN0 to AN7). The pins function as an analog input if the
corresponding bit in the port data register (PDR5) is set to "1" to turn "OFF" the output transistor
and the pin is selected in the analog input channel selection bits (ADC1: ANS0 to ANS3). Even
when the A/D converter is in use, pins not used as analog inputs can be used as output-only
ports.
AN0 to AN7: When using the A/D conversion or sense function, input the analog voltage to
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CHAPTER 13 A/D CONVERTER
input the external clock to this pin.
output pin (CLKO) on a product with the clock monitor function.
PDR
(Port data register)
PDR read
PDR read (for bit manipulation instructions)
Output latch
PDR write
DDR
DDR write

Figure 13.3a Block Diagram of P30/ADST Pin

be converted or compared to these pins.
Input clock selector for
A/D converter activation
Input buffer
Output buffer
(Port data direction register)
Stop mode (SPL = "1")
Pull-up resistor
(optional)
Approx. 50 k Ω /5.0 V
Pin
P30/ADST
(P30/ADST/CLKO)
MB89620 series