Figure 3.8.6 Hold Operation - Fujitsu F2MC-8L MB89620 Series Hardware Manual

3.8 Memory Access Modes
3.8.6 Hold Operation
In external bus mode, the CPU releases the external bus pins in response to a hold
request from an external peripheral function. This hold operation allows the external
peripheral function to use the bus.
n Hold Operation
• Set the hold enable bit in the external bus pin control register (BCTR: HLD) to "1" to enable
the hold function.
• The CPU reads the state of the hold request (HRQ) pin between each instruction (CPU
cycle). On detecting an "H" level on the HRQ pin due to a request from an external
peripheral function or similar, the CPU temporarily halts operation and sets the address pins
(A08 to A15), data pins (AD0 to AD7), RD pin, WR pin, RDY pin, and BUFC pin to
high-impedance state. After a dead cycle, the CPU outputs an "L" level from the hold
acknowledge (HAK) pin to notify that it has opened the external bus.
• On completing use of the external bus, the external device returns the HRQ pin to the "L"
level. On detecting that the HRQ pin is at the "L" level, the CPU sets the HAK pin to the "H"
level then restarts use of the external bus after the completion of a dead cycle.
• Hold requests (HRQ) are not accepted in sleep or stop mode.
• The hold function stops the CPU but internal peripheral functions continue to operate.
However, the watchdog timer counter is cleared so that no watchdog reset occurs.
Figure 3.8.6 shows the hold operation.
Reference: See Appendix E, "MB89620 Series Pin States" for pin states during hold operation.
86
CHAPTER 3 CPU
CLK
ALE
A08
Upper address
to A15
AD0
Lower
address
to AD7
RD
WR
BUFC
HRQ
HAK
CPU cycles

Figure 3.8.6 Hold Operation

Data
Dead cycle
Hold operation
Completion of one instruction
Upper address
Lower
Data
address
CPU cycles
Dead cycle
MB89620 series