Figure 9.6A Counter Function Settings; Figure 9.6B Operation Of 16-Bit Counter; Operation Of Counter Function - Fujitsu F2MC-8L MB89620 Series Hardware Manual

6
9.

Operation of Counter Function

This section describes the operation of the counter function of the 16-bit timer/counter.
n Operation of Counter Function
Figure 9.6a shows the settings required to operate the counter function.
On activation (TMCR: TCS = "1"), the counter counts-up each time the specified edge is
detected on pulses input to the EC pin (external count clock) from the TCR register value.
When the counter value overflows (FFFF
request flag bit (TMCR: TCEF = "1").
Then, the counter restarts counting-up from "0000
Figure 9.6b shows the counter operation when the counter operation mode selection bits
(TMCR: TCS1, TCS0) are set to "11
"0000 ".
H
External input pulses
(input waveform to the EC pin)
Counter value
TCEF bit
TCS bit
Check: Do not write to the TCR register while the counter function is operating (TMCR: TCS = "1").
MB89620 series
Bit 7 Bit 6
DDR3
× ×
TMCR — —
TCHR
TCLR

Figure 9.6a Counter Function Settings

FFFF
H
0000
H

Figure 9.6b Operation of 16-bit Counter

Bit 5 Bit 4 Bit 3
× ×
0
TCR TCS1 TCS0
1 Other than "00"
Sets the counter initial value (upper 8 bits).
Sets the counter initial value (lower 8 bits).
→ 0000
), the 16-bit timer/counter sets the interrupt
H H
" when the next specified edge is input.
H
" (detect both edges) and the TCR register is set to
B
. . . . . . .
. . . . . . .
CHAPTER 9 16-BIT TIMER/COUNTER
Bit 2 Bit 1 Bit 0
× × ×
TCEF TCIE TCS
× : Unused bit
1 : Set "1".
0 : Set "0".
Cleared by program
: Used bit
191