16-Bit Timer/Counter Interrupts - Fujitsu F2MC-8L MB89620 Series Hardware Manual

4
9.

16-bit Timer/Counter Interrupts

The 16-bit timer/counter has the following two interrupts:
• Overflow (FFFF
• Overflow (FFFF
n Interrupt for Interval Timer Function
The counter value is counted-up from the set value on the internal count clock. When an
overflow occurs, the interrupt request flag bit (TMCR: TCEF) is set to "1". At this time, an
interrupt request (IRQ6) to the CPU is generated if the interrupt request enable bit is enabled
(TMCR: TCIE = "1").
Write "0" to the TCEF bit in the interrupt processing routine to clear the interrupt request.
Notes: • The TCEF bit is not set if the counter is cleared (TMCR: TCR = "0") at the same time as the
counter value overflows. An interrupt request is generated immediately if the TCEF bit is "1" when
the TCIE bit is changed from disabled to enabled ("0" → "1").
• The TCEF bit is set when the counter value overflows, regardless of the TCIE bit value.
n Interrupt for Counter Function
The counter value is counted-up from the set value each time it detects a specified edge. When
an overflow occurs, the interrupt request flag bit (TMCR: TCEF) is set to "1". At this time, an
interrupt request (IRQ6) to the CPU is generated if the interrupt request enable bit is enabled
(TMCR: TCIE = "1").
Write "0" to the TCEF bit in the interrupt processing routine to clear the interrupt request.
Notes: • The TCEF bit is not set if the counter is cleared (TMCR: TCR = "0") at the same time as the
counter value overflows. An interrupt request is generated immediately if the TCEF bit is "1" when
the TCIE bit is changed from disabled to enabled ("0" → "1").
• The TCEF bit is set when the counter value overflows, regardless of the TCIE bit value.
n Register and Vector Table for 16-bit Timer/Counter Interrupt
Table 9.4 Register and Vector Table for 16-bit Timer/Counter Interrupt
Interrupt
IRQ6
Reference: See Section 3.4.2, "Interrupt Processing" for details on the interrupt operation.
MB89620 series
→ 0000
) for the interval timer function
H H
→ 0000
) for the 16-bit counter function
H H
Interrupt level setting register
Register
ILR2 (007D ) L61 (Bit 5)
H
Setting bits
L60 (Bit 4)
CHAPTER 9 16-BIT TIMER/COUNTER
Vector table address
Upper Lower
FFEE FFEF
H H
189