Fujitsu F2MC-8L MB89620 Series Hardware Manual page 226

Table 10.3.1 Serial 1 Mode Register (SMR1) Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MB89620 series
Bit
• This bit is set to "1" when the serial output operation has output 8 bits of serial
data or the serial input operation has input 8 bits of serial data.
SIOF:
An interrupt request is output when both this bit and the interrupt request enable
Interrupt request flag
bit (SIOE) are "1".
bit
• Writing "0" clears this bit. Writing "1" has no effect and does not change the bit
value.
SIOE: This bit enables or disables an interrupt request output to the CPU. An interrupt
Interrupt request request is output when both this bit and the interrupt request flag bit (SIOF) are
enable bit "1".
• This bit controls the shift clock input and output.
• The P31/SCK1 pin functions as the shift clock input pin when this bit is set to "0"
and as the shift clock output pin when set to "1".
Check: • Set the P31/SCK1 pin as an input port when using this pin as the shift
SCKE:
Shift clock output
enable bit
Notes: • The pin functions as the SCK1 output pin when shift clock is enabled
The P32/SO1 pin functions as a general-purpose port (P32) when this bit is set to
SOE:
"0" and as the serial data output pin (SO1) when set to "1".
Serial data output
Note: The pin functions as the SO1 pin when serial data output is enabled (SOE=
enable bit
• These bits select the shift clock from one external and three internal shift
clocks.
• Setting these bits to other than "11
CKS1, CKS0:
the shift clock is output from the SCK1 pin if the shift clock output enable bit
Shift clock selection
(SCKE) is "1".
bits
• Setting these bits to "11
clock from the SCK1 pin if shift clock input is enabled (SCKE = "0" and DDR3:
bit 1 = "0").
This bit selects whether serial data is transferred with the least significant bit first
BDS: (LSB first, BDS = "0") or the most significant bit first (MSB first, BDS = "1").
Transfer direction Check: As bits are set in the appropriate order when writing to or reading from the
selection bit
• This bit controls serial I/O transfer start and transfer enable. This bit can also be
used to determine whether transfer has completed.
• Writing "1" to this bit when an internal shift clock is selected (CKS1, CKS0 =
other than "11
SST: • Writing "1" to this bit when an external shift clock is selected (CKS1, CKS0 =
Serial I/O transfer "11
start bit to delay for input of the external shift clock.
• This bit is cleared to "0" and the SIOF bit set to "1" when transfer completes.
• Writing "0" to this bit while transfer is in progress (SST = "1") aborts the transfer.
After halting a transfer, data must be set again to the SDR register for data
output and transfer restarted (the shift clock counter cleared) for data input.
CHAPTER 10 8-BIT SERIAL I/O (SERIAL I/O-1 AND SERIAL I/O-2)
Function
clock input. Also, selects external shift clock operation in the shift clock
selection bits (CKS1, CKS0 = "11
• Select internal shift clock operation (CKS1, CKS0 = other than "11
when using this pin as a shift clock output (SCKE = "1").
(SCKE = "1"), regardless of the state of the general-purpose port (P31).
• Set to shift clock input operation (SCKE = "0") when using this pin as a
general-purpose port (P31).
"1"), regardless of the state of the general-purpose port (P32).
" selects the external shift clock. This inputs the shift
B
serial 1 data register (SDR1), modifying this bit does not apply to any data
already set in the SDR1 register.
") clears the shift clock counter and starts data transfer.
B
") enables data transfer, clears the shift clock counter, and sets serial I/O-1
B
").
B
" selects an internal shift clock. In this case,
B
")
B
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