Fujitsu F2MC-8L MB89620 Series Hardware Manual page 13

Figure 3.7.3 Standby Control Register (STBC) ........................................................................................ 70
Figure 3.7.4a State Transition Diagram for Products with Power-on Reset ............................................ 72
Figure 3.7.4b State Transition Diagram for Products without Power-on Reset ....................................... 72
Figure 3.8 Memory Map in Each Mode .................................................................................................... 77
Figure 3.8.1a Mode Data Structure .......................................................................................................... 78
Figure 3.8.1b Memory Access Selection Operation ................................................................................. 79
Figure 3.8.3 External Bus Pin Control Register (BCTR) .......................................................................... 81
Figure 3.8.4a External Bus Operation (Bus Cycle) .................................................................................. 82
Figure 3.8.4b Example of Connecting External Memory and Peripheral Function .................................. 83
Figure 3.8.5a Ready Operation ................................................................................................................ 84
Figure 3.8.5b Ready Signal Generator .................................................................................................... 84
Figure 3.8.5c Ready Signal Generation Timing ....................................................................................... 85
Figure 3.8.6 Hold Operation..................................................................................................................... 86
CHAPTER 4 I/O PORTS ...................................................................................................... 87
Figure 4.2 Block Diagram of Port 0 and 1 Pin (Single-chip Mode) .......................................................... 91
Figure 4.3 Block Diagram of Port 2 Pin (Single-chip Mode) .................................................................... 95
Figure 4.4 Block Diagram of Port 3 Pin .................................................................................................... 99
Figure 4.5 Block Diagram of Port 4 Pin .................................................................................................. 105
Figure 4.6 Block Diagram of Port 5 Pin .................................................................................................. 109
Figure 4.7 Block Diagram of Port 6 Pin .................................................................................................. 112
Figure 4.8 Connection Example for an Eight Segment LED .................................................................. 116
CHAPTER 5 TIMEBASE TIMER ........................................................................................ 117
Figure 5.2 Block Diagram of Timebase Timer ....................................................................................... 119
Figure 5.3 Timebase Timer Control Register (TBTC) ............................................................................ 120
Figure 5.5a Interval Timer Function Settings ......................................................................................... 124
Figure 5.5b Timebase Timer Operation ................................................................................................. 125
Figure 5.6 Effect on Buzzer Output of Clearing Timebase Timer .......................................................... 126
CHAPTER 6 WATCHDOG TIMER ..................................................................................... 129
Figure 6.2 Block Diagram of Watchdog Timer ....................................................................................... 131
Figure 6.3 Watchdog Timer Control Register (WDTC) .......................................................................... 132
Figure 6.4 Watchdog Timer Clear and Interval Time (For a 10 MHz source oscillation) ....................... 133
CHAPTER 7 8-BIT PWM TIMER ....................................................................................... 137
Figure 7.1 Example D/A Converter Configuration Using PWM Output and Low Pass Filter ................. 139
Figure 7.2 Block Diagram of 8-bit PWM Timer ...................................................................................... 140
Figure 7.3a Block Diagram of 8-bit PWM Timer Pin .............................................................................. 142
Figure 7.3b 8-bit PWM Timer Registers ................................................................................................. 143
Figure 7.3.1 PWM Control Register (CNTR) .......................................................................................... 144
Figure 7.3.2 PWM Compare Register (COMR) ..................................................................................... 146
MB89620 series
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