Fujitsu F2MC-8L MB89620 Series Hardware Manual page 132

4.6 Port 5
4.6.2 Operation of Port 5
This section describes the operations of the port 5.
n Operation of Port 5
Operation as an output port
l
• Writing data to the PDR5 register stores the data in the output latch. When the output latch
value is "0", the output transistor turns "ON" and an "L" level is output from the pin. When the
output latch value is "1", the transistor turns "OFF" and the pin goes to the high-impedance
state. If a pull-up is provided the output pin the pin goes to the pull-up state when the output
latch value is "1".
• Reading the PDR5 register always returns the output latch value.
l Operation as an analog input
Write "1" to the corresponding bit of the PDR5 register if using a pin as an analog input. This
turns the output transistor "OFF" and sets the pin to the high-impedance state.
Operation at reset
l
Resetting the CPU initializes the PDR5 register values to "1". This turns all the output transistors
"OFF" and sets the pins to the high-impedance state.
Operation in stop mode
l
The output transistors are forcibly turned "OFF" and the pins go to the high-impedance state if
the pin state specification bit in the standby control register (STBC: SPL) is "1" when the device
changes to stop mode.
Table 4.6.2 lists the port 5 pin states.
Table 4.6.2 Port 5 Pin State
Pin name
P50/AN0 to P57/AN7
SPL: Pin state specification bit in the standby control register (STBC)
Hi-z: High impedance
Note: Pins with a pull-up resistor (optional) go to the "H" level (pull-up state) rather than to the high-
impedance state when the output transistor is turned "OFF".
MB89620 series
Normal operation
Sleep mode
Stop mode (SPL=0)
Output-only ports/analog input
Stop mode
(SPL=1)
Hi-z
CHAPTER 4 I/O PORTS
Reset
Hi-z
111