Figure 14.3 Block Diagram Of P30/Adst/Clko Pin; Structure Of Clock Monitor Function - Fujitsu F2MC-8L MB89620 Series Hardware Manual

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14.

Structure of Clock Monitor Function

This section describes the pin, pin block diagram, and register of the clock monitor
function.
n Clock Monitor Function Pin
The clock monitor function uses the P30/ADST/CLKO pin. This pin can function as either a
general-purpose I/O port (P30), as the external clock input used to activate the A/D conversion
(ADST), or as the clock output (CLKO).
Setting the P30/ADST/CLKO pin as a clock output in the clock output control bit (CLKE: CLKEN
= "1") automatically.
CLKO: A clock signal consisting of the divide-by-two source oscillation is output to this pin.
n Block Diagram of Clock Monitor Function Pin
SPL: Pin state specification bit in the standby control register (STBC)
Note: Pins with a pull-up resistor (optional) go to the "H" level during a reset or in stop mode (SPL = "1").
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CHAPTER 14 CLOCK MONITOR FUNCTION
Set the pin as output, regardless of the port data direction register (DDR3: bit 0)
value, and sets the pin to function as the CLKO pin.
Clock output
PDR
(Port data register)
PDR read
PDR read (for bit manipulation instructions)
Output latch
PDR write
DDR
(Port data direction register)
DDR write

Figure 14.3 Block Diagram of P30/ADST/CLKO Pin

Clock output
enable signal
Input buffer
Output buffer
Clock output
selector
Stop mode (SPL = "1")
ADST
Pull-up resistor
(optional)
Approx. 50 k Ω /5.0 V
Pin
P30/ADST
/CLKO
MB89620 series