Pulse Width Count Timer Interrupts; Function - Fujitsu F2MC-8L MB89620 Series Hardware Manual

4
8.

Pulse Width Count Timer Interrupts

The pulse width count timer has the following two interrupts:
• Counter value underflow (01
• Measurement completion and buffer full for the pulse width measurement

function

n Interrupt for the Interval Timer Function
The counter value is counted-down from the set value on the selected internal count clock.
When an underflow occurs, the underflow (01
set to "1". At this time, an interrupt request (IRQ5) to the CPU is generated if the interrupt
request enable bit is enabled (PCR1: IE = "1"). Write "0" to the UF bit in the interrupt processing
routine to clear the interrupt request.
Notes: • The UF bit is not set if the counter is stopped (PCR1: EN = "0") at the same time as a counter
• An interrupt request is generated immediately if the UF bit is "1" when the IE bit is changed from
n Interrupt for Pulse Width Measurement Function
When the specified measurement completion edge is detected, the measurement completion
interrupt request flag bit (PCR1: IR) and the buffer full flag bit (PCR1: BF) are set to "1". Also,
when a counter underflow (01
set to "1". At this time, an interrupt request (IRQ5) to the CPU is generated if the interrupt
request enable bit is enabled (PCR1: IE = "1"). Write "0" to the IR and UF bits in the interrupt
processing routine to clear the interrupt request. Also read the PWC reload buffer register
(RLBR) to clear the BF bit to "0".
Notes: • The IR and BF bits are not set if the counter is stopped (PCR1: EN = "0") at the same time as a
• An interrupt request is generated immediately if the IR, BF, or UF bit is "1" when the IE bit is
n Register and Vector Table for Pulse Width Count Timer Interrupt
Table 8.4 Register and Vector Table for Pulse Width Count Timer Interrupt
Interrupt
IRQ5
Reference: See Section 3.4.2, "Interrupt Processing" for details on the operation of interrupt.
MB89620 series
→ 00
H
→ 00
value underflows (01
H
disabled to enabled ("0" → "1").
→ 00
H
the specified measurement completion edge is detected.
changed from disabled to enabled ("0" → "1").
Interrupt level setting register
Register
ILR2 (007D )
H
) for the interval timer function
H
→ 00
) interrupt request flag bit (PCR1: UF) is
H H
).
H
) occurs due to measurement of a long pulse the UF bit is
H
Setting bits
L51 (Bit 3) L50 (Bit 2)
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC)
Vector table address
Upper Lower
FFF0 FFF1
H H
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