Figure 13.3B Block Diagram Of P57/An7 To P50/An0 Pins; Figure 13.3C A/D Converter Registers - Fujitsu F2MC-8L MB89620 Series Hardware Manual

Figure 13.3b shows the block diagram of the P57/AN7 to P50/AN0 pins.
SPL: Pin state specification bit in the standby control register (STBC)
Check: Do not set with a pull-up resistor as an option for any of the P57/AN7 to P50/AN0 pins if using the
A/D converter.
n A/D Converter Registers
ADC1 (A/D control register 1)
ADC2 (A/D control register 2)
ADCD (A/D data register)
R/W : Readable and writable
R : Read-only
— : Unused
X : Indeterminate
n A/D Converter Interrupt Source
IRQ9: The A/D converter generates an interrupt request if an interrupt request output is enabled
(ADC2: ADIE = "1") when A/D conversion completes or the sense function detects the
specified condition.
MB89620 series
(Port data register)
PDR
PDR read
Output latch
PDR write
Stop mode (SPL = "1")

Figure 13.3b Block Diagram of P57/AN7 to P50/AN0 Pins

Address Bit 7 Bit 6
0020 ANS3 ANS2
H
R/W R/W
Address Bit 7 Bit 6
0021 — —
H
Address Bit 7 Bit 6
0022
H
R/W R/W

Figure 13.3c A/D Converter Registers

A/D converter
channel select signal
To sample hold circuit
Output Tr
Bit 5 Bit 4 Bit 3 Bit 2
ANS1 ANS0 ADI ADMV
R/W R/W R/W R
Bit 5 Bit 4 Bit 3 Bit 2
— ADCK ADIE ADMD
R/W R/W R/W
Bit 5 Bit 4 Bit 3 Bit 2
R/W R/W R/W R/W
CHAPTER 13 A/D CONVERTER
Pull-up resistor
(optional)
Approx. 50 kΩ/5.0 V
Pin
P57/AN7, P56/AN6
P55/AN5, P54/AN4
P53/AN3, P52/AN2
P51/AN1, P50/AN0
Bit 1 Bit 0 Initial value
SIFM AD 00000000
B
R/W R/W
Bit 1 Bit 0 Initial value
EXT RESV1 XXX00001
B
R/W R/W
Bit 1 Bit 0 Initial value
XXXXXXXX
B
R/W R/W
249
13