Table 4.4.1 Port 3 Register Function - Fujitsu F2MC-8L MB89620 Series Hardware Manual

4.4 Port 3
4.4.1 Port 3 Registers (PDR3, DDR3)
This section describes the port 3 registers.
n Port 3 Register Functions
l Port 3 data register (PDR3)
The PDR3 register holds the pin states.
Port 3 data direction register (DDR3)
l
The DDR3 register sets the direction (input or output) for each pin (bit).
Setting "1" to the bit corresponding to a port (pin) sets the pin as an output port. Setting "0" sets
the pin as an input port.
Check: As the DDR3 register is write-only, the bit manipulation instructions (SETB and CLRB) cannot be
Notes: • When using peripherals that have output pins, enabling a peripheral's output enable bit, for a
Table 4.4.1 lists the functions of the port 3 registers.

Table 4.4.1 Port 3 Register Function

Register
Port 3 data register
(PDR3)
Port 3 data direction
register (DDR3)
R/W : Readable and writable
W : Write-only
X : Indeterminate
100
CHAPTER 4 I/O PORTS
used.
particular pin, sets that pin as a peripheral output pin, regardless of the DDR3 register setting
value.
• When using peripherals that have input pins, set the DDR3 register bits corresponding to the
peripheral input pins to "0" to set the pins as input ports.
• Writing data to the PDR3 register for pins that have been set to the input direction does not output
to the pins. (However, the data is held in the output latch.) Also, the DDR3 register is initialized to
"0" by a reset.
Data
Pin state is the "L"
0
level.
Pin state is the "H"
1
level.
0
Reading is not
permitted (write-
only).
1
Read Write
Sets "0" to the output
latch.
Outputs an "L" level to
the pin if the pin
functions as an output
port.
Sets "1" to the output
latch.
Outputs an "H" level to
the pin if the pin
functions as an output
port.
Sets the output buffer
"OFF" and sets the pin
as an input pin.
Sets the output buffer
"ON" and sets the pin as
an output pin.
Read/
Address Initial value
Write
R/W 000C XXXXXXXX
H
W 000D 00000000
H
MB89620 series
B
B