Fujitsu F2MC-8L MB89620 Series Hardware Manual page 77

3.5 Reset
3.5.3 Pin States During Reset
The mode pin (MOD1, MOD0) values determine the pin states and select the location
from which the mode data is read.
n Pin States during Reset
When the mode pin (MOD1, MOD0) levels are "V
high- impedance state and the mode data is read from internal ROM (Pins with a pull-up resistor
(optional) go to the "H" level).
When the mode pin (MOD1, MOD0) levels are "V
to ports 0 and 1 become indeterminate and the external bus control pins corresponding to port 2
go to the operating state and the pin states are established. Other I/O pins go to high-
impedance state and the mode data is read from external ROM. (Pins with a pull-up resistor
(optional) go to the "H" level.)
n Pin States after Reading Mode Data
Ports 0 and 1 become available as general-purpose I/O ports when the mode data is 00
(single-chip mode). However, the pins remain in the high-impedance state immediately after
reading the mode data. (Pins with a pull-up resistor (optional) go to the "H" level.)
Port 2 can be used as an output-only port. Output is enabled and the ports output the "L" level
immediately after reading the mode data.
Ports 0 and 1 become external bus pins and the port 2 function as external bus control pins
when the mode data is 01
internal ROM, the port 0, port 1, and port 2 pins change from high-impedance state to their
respective operating states.
Check: For devices connected to pins that change to high-impedance state when a reset source occurs,
Reference: See Appendix E, "MB89620 Series Pin States" for pin states at times other than a reset.
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CHAPTER 3 CPU
(external bus mode). Therefore, if the mode data is read from
H
take care that malfunction does not occur due to the change in the pin states.
, V ", all I/O pins (peripheral pins) go to the
SS SS
, V ", the external bus pins corresponding
SS CC
H
MB89620 series