Fujitsu F2MC-8L MB89620 Series Hardware Manual page 142

Table 5.3 Timebase Timer Control Register (TBTC) Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MB89620 series
Bit
• The read value is indeterminate.
Unused bits
• Writing to these bits has no effect on the operation.
TBIE: This bit enables or disables an interrupt request output to the CPU. An interrupt
Interrupt request request is output when both this bit and the overflow interrupt request flag bit
enable bit (TBOF) are "1".
• This bit is set to "1" when an overflow occurs on the specified bit of the timebase
timer counter.
TBOF:
• An interrupt request is output when both this bit and the interrupt request enable
Overflow interrupt
bit (TBIE) are "1".
request flag bit
• Writing "0" clears this bit. Writing "1" has no effect and does not change the bit
value.
This bit clears the timebase timer counter.
TBR:
Writing "0" to this bit clears the counter to 00000
Timebase timer
does not change the bit value.
initialization bit
Note: The read value is always "1".
These bits select the cycle of the interval timer.
TBC1, TBC0:
These bits select which bit of the timebase timer counter to use as the interval
Interval time
timer bit.
selection bits
Four different interval times can be selected.
Function
. Writing "1" has no effect and
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CHAPTER 5 TIMEBASE TIMER
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