Fujitsu F2MC-8L MB89620 Series Hardware Manual page 76

n Mode Pins
When a reset source occurs, pins related to the external bus mode (port 0, port 1, and port 2)
are initialized according to the memory access mode specified by the mode pins (MOD1,
MOD0). The mode pin settings determine whether the mode data and reset vector are read
from internal or external ROM.
Do not change the mode pin settings, even after the reset has completed.
n Mode Fetch
When the CPU wakes up from a reset, the CPU reads the mode data and reset vector from the
location (internal or external ROM) selected by the mode pin settings.
l Mode data (address: FFFD
Selects single-chip mode or external bus mode. If external bus mode is selected when the mode
data is read from internal ROM, port 0, port 1, and port 2 become the external bus pins and the
pin states are modified.
Always set external bus mode if the mode data is read from external ROM.
Reference: See Section 3.8, "Memory Access Modes" for details.
Reset vector (address: FFFE
l
Contains the address where execution is to start after completion of the reset. The CPU starts
executing instructions from the address contained in the reset vector.
n Oscillation Stabilization Delay Reset State
On products with power-on reset, the reset operation for a power-on reset or external reset in
stop mode starts after the oscillation stabilization delay time determined by the timebase timer.
If the CPU has not waked up from the external reset input when the delay time completes, the
reset operation does not start until the CPU wakes up from external reset.
As the oscillation stabilization delay time is also required when an external clock is used, a reset
requires that the external clock is input.
On products without power-on reset, the oscillation stabilization delay reset state is not used.
Therefore, for such products, hold the external reset pin (RST) at the "L" level to disable the
CPU operation until the source oscillation stabilizes.
n Effect of Reset on RAM Contents
The contents of RAM are unchanged before and after a reset other than power-on reset.
As detection of an external reset is synchronized with the internal clock on products with power-
on reset, writes complete normally even if an external reset is input during a write operation.
However, if a reset occurs during writing of 16-bit data, it is possible that only the upper byte
write completes and the lower byte write does not occur.
If an external reset is input close to a write timing on products without power-on reset, the
contents of the write address cannot be assured.
MB89620 series
)
H
(upper), FFFF (lower))
H H
55
CHAPTER 3 CPU