Fujitsu F2MC-8L MB89620 Series Hardware Manual page 95

3.7 Standby Modes (Low-power Consumption)
3.7.6 Notes on Using Standby Modes
The CPU does not change to a standby mode if an interrupt request occurs from a
peripheral function when a standby mode is set in the standby control register (STBC).
Also, if an interrupt is used to wake up from a standby mode to the normal operating
state, the operation after wake-up differs depending on whether or not the interrupt
request is accepted.
n Changing to a Standby Mode and Interrupts
If an interrupt request with an interrupt level higher than "11" occurs from a peripheral function to
the CPU, writing "1" to the stop bit (STP) or sleep bit (SLP) in the standby control register
(STBC) is ignored. Therefore, the CPU does not change to a standby mode. (The CPU also
does not change to the standby mode after completing interrupt processing.)
This does not depend on whether or not the CPU accepts the interrupt.
Even if the CPU is currently performing interrupt processing, the interrupt request flag bit is
cleared and, if no other interrupt request is present, the device can change to a standby mode.
n Wake-up from Standby Mode by Interrupt
If an interrupt request with an interrupt level higher than "11" occurs from a peripheral function
or others during sleep or stop mode, the CPU wakes up from a standby mode. This does not
depend on whether or not the CPU accepts the interrupt.
After wake-up from a standby mode, the CPU performs the normal interrupt operations. If the
level set in the interrupt level setting register (ILR1 to ILR3) corresponding to the interrupt
request is higher than the interrupt level bits in the condition code register (CCR: IL1, IL0), and if
the interrupt enable flag is enabled (CCR: I = "1"), the CPU branches to the interrupt processing
routine. If the interrupt is not accepted, operation restarts from the instruction following the
instruction that activated a standby mode.
To prevent control from branching to an interrupt processing routine after wake-up, take
measures such as disabling interrupts before setting a standby mode.
n Notes on Setting Standby Mode
Sleep bit and stop bit are mutually exclusive; set either bit, sleep bit (STBC: SLP) or stop bit
(STBC: STP), in the standby control register to "1". (Writing "1" to both bits means the change to
stop mode.)
n Oscillation Stabilization Delay Time
As the oscillator that provides the source oscillation is stopped during stop mode, a delay time is
required for oscillation to stabilize after the oscillator restarts operation. The oscillation
stabilization delay time (optional) can be set by specifying the oscillation stabilization delay time
bit in the timebase timer counter.
If the interval time set for the timebase timer is less than the oscillation stabilization delay time,
the timebase timer generates an interval timer interrupt request before the end of the oscillation
stabilization delay time. To prevent this, disable the interrupt request output for the timebase
timer (TBTC: TBIE = "0") before changing to stop mode as necessary.
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CHAPTER 3 CPU
MB89620 series