Figure 10.8D Operation In Sleep Mode (External Shift Clock); Figure 10.8E Operation In Stop Mode (External Shift Clock); Figure 10.8F Operation During Halt (External Shift Clock) - Fujitsu F2MC-8L MB89620 Series Hardware Manual

n Using External Shift Clock
l Operation in sleep mode
In sleep mode, serial I/O operation does not halt but transfer continues, as shown in Figure
10.8d.
l Operation in stop mode
In stop mode, serial I/O operation halts and transfer aborts, as shown in Figure 10.8e.
Operation restarts from the point where it halted after wake-up from stop mode. This causes an
error to occur on the device with which the 8-bit serial I/O is communicating. Initialize the 8-bit
serial I/O after wake-up from stop mode.
Operation during halt
l
Halting operation during transfer (SMR: SST = "0") halts the transfer and clears the shift clock
counter, as shown in Figure 10.8f. Therefore, the device being communicated with must also be
initialized. In serial output operation, set the SDR register again before reactivating. If an
external clock is input at this time, the SO pin output changes.
MB89620 series
SCK input
SST bit
SIOF bit
SO pin output
#0 #1
SLP bit
(STBC register)

Figure 10.8d Operation in Sleep Mode (External Shift Clock)

SCK input
SST bit
SIOF bit
SO pin output
#0 #1
STP bit
(STBC register)

Figure 10.8e Operation in Stop Mode (External Shift Clock)

SCK input
SST bit
SIOF bit
SO pin output
#0 #1

Figure 10.8f Operation during Halt (External Shift Clock)

CHAPTER 10 8-BIT SERIAL I/O (SERIAL I/O-1 AND SERIAL I/O-2)
#2 #3 #4 #5 #6
Sleep mode
Wake-up from sleep mode by IRQ7 or IRQ8.
#6 #7
Stop request
#2 #3 #4 #5
Stop mode
Wake-up from stop mode by an external interrupt.
#6 #7
Operation halts
Reset SDR register
#2 #3 #4 #5
Clock for next data
Transfer disabled state
Cleared by the program.
#7
Clock for next data
Oscillation
stabilization
delay time Cleared by the program.
Interrupt request
#6 #7
Transfer error occurs.
Clock for next data
Operation reactivates.
#0 #1
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