Figure 13.5A A/D Conversion Function (Software Activation) Settings; Figure 13.5B A/D Conversion Function (Continuous Activation) Settings; A/D Converter Operation - Fujitsu F2MC-8L MB89620 Series Hardware Manual

5
13.

A/D Converter Operation

The A/D conversion and sense functions of the A/D converter can be activated by
software or can be activated continuously.
n Activating A/D Conversion Function
Software activation
l
Figure 13.5a shows the settings required for software activation of the A/D conversion function.

Figure 13.5a A/D Conversion Function (Software Activation) Settings

On activation, the A/D converter starts the operation of the A/D conversion function. The A/D
conversion function can be reactivated while conversion is in progress.
l Continuous activation
Figure 13.5b shows the settings required for continuous activation of the A/D conversion function.

Figure 13.5b A/D Conversion Function (Continuous Activation) Settings

When continuous activation is enabled, the rising edge of the selected input clock activates the
A/D conversion, starting operation of the A/D conversion function. When continuous activation is
disabled (ADC2: EXT = "0"), continuous activation halts but software activation is available.
n Operation of A/D Conversion Function
The following describes the operation of the A/D converter. From activation to completion of A/D
conversion requires approximately 44 instruction cycles.
(1) On activation, A/D conversion sets the conversion-in-progress flag bit (ADC1: ADMV = "1")
and connects the sample hold circuit to the specified analog input pin.
(2) The internal sample hold capacitor captures the voltage at the analog input pin for
approximately 8 instruction cycles. The capacitor holds the voltage until the A/D conversion
completes.
(3) The comparator compares the voltage captured by the sample hold capacitor with the A/D
converter reference voltage starting from the most significant bit (MSB) and ending with the
least significant bit (LSB), and transfers each bit sequentially to the ADCD register.
(4) When the complete result has been transferred to the ADCD register, the conversion-in-
progress flag bit is cleared (ADC1: ADMV = "0") and the interrupt request flag bit is set (ADC1:
ADI = "1").
256
CHAPTER 13 A/D CONVERTER
Bit 7 Bit 6
ADC1 ANS3 ANS2
0
ADC2 — —
ADC3
Bit 7 Bit 6
ADC1 ANS3 ANS2
0
ADC2 — —
ADC3
Bit 5 Bit 4 Bit 3 Bit 2
ANS1 ANS0 ADI ADMV
— ADCK ADIE ADMD
×
Stores the A/D conversion result.
Bit 5 Bit 4 Bit 3 Bit 2
ANS1 ANS0 ADI ADMV
— ADCK ADIE ADMD
Stores the A/D conversion value.
Bit 1 Bit 0
SIFM AD
×
1
EXT RESV1
: Used bit
0 0 1
× : Unused bit
1 : Set "1".
0 : Set "0".
Bit 1 Bit 0
SIFM AD
× ×
EXT RESV1
: Used bit
0 1 1
× : Unused bit
1 : Set "1".
0 : Set "0".
MB89620 series