Fujitsu F2MC-8L MB89620 Series Hardware Manual page 123

4.4 Port 3
4.4.2 Operation of Port 3
This section describes the operations of the port 3.
n Operation of Port 3
l Operation as an output port
• Setting the corresponding DDR3 register bit to "1" sets a pin as an output port.
• When a pin is set as an output port, the output buffer is "ON" and the pin outputs the data
stored in the output latch.
• Writing data to the PDR3 register stores the data in the output latch and outputs the data
directly to the pin.
• Reading the PDR3 register returns the pin value ("0" or "1", the same value as the output
latch).
Note: As the bit manipulation instructions (SETB and CLRB) read the output latch data rather than the pin
level, the instructions do not change the output latch values for bits other than the bit being set or
cleared.
l Operation as an input port
• Setting the corresponding DDR3 register bit to "0" sets a pin as an input port.
• When a pin is set as an input port, the output buffer is "OFF" and the pin goes to the
high-impedance state.
• Writing data to the PDR3 register stores the data in the output latch but does not output the
data to the pin.
• Reading the PDR3 register returns the pin value ("0" or "1").
Operation as a peripheral output
l
Set the output enable bit of the peripheral to use a pin as a peripheral output. As the output
enable bit of the peripheral has priority when determining whether a pin is an input or output, the
pin functions as a peripheral output if the peripheral output is enabled, even if the DDR3 register
bit is set to "0". As the pin value can be read even if the peripheral output is enabled, the
peripheral output value can be read.
l Operation as a peripheral input
The pin value is continuously input for ports that also serve as a pin with a peripheral input,
regardless of the DDR3 register setting value and of whether or not the peripheral is using the
input pin. When the peripheral is using the external signal, set the DDR3 register bit to "0" to set
the port as an input.
Operation at reset
l
• Resetting the CPU initializes the DDR3 register values to "0". This sets all output buffers
"OFF" (all pins become input ports) and sets the pins to the high-impedance state.
• The PDR3 register is not initialized by a reset. Therefore, to use as output ports, the output
data must be set in the PDR3 register before setting the corresponding DDR3 register bits to
output mode.
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CHAPTER 4 I/O PORTS MB89620 series