Fujitsu F2MC-8L MB89620 Series Hardware Manual page 337

EIE2 (Interrupt request enable bit 2) ...........................................................................................................238
EIE3 (Interrupt request enable bit 3) ...........................................................................................................238
EIR0 (External interrupt request flag bit 0) ..................................................................................................236
EIR1 (External interrupt request flag bit 1) ..................................................................................................236
EIR2 (External interrupt request flag bit 2) ..................................................................................................238
EIR3 (External interrupt request flag bit 3) ..................................................................................................238
EN (Counter operation enable bit) ...............................................................................................................164
EP (Extra pointer) ..........................................................................................................................................36
EXT (Continuous activation enable bit) .......................................................................................................252
F
FC (Operating mode selection bit) ...............................................................................................................166
H
H (Half-carry flag) ..........................................................................................................................................38
HLD (Hold enable bit) ....................................................................................................................................81
I
I (Interrupt enable flag) ..................................................................................................................................38
IE (Interrupt request enable bit) ...................................................................................................................164
IL0 (Interrupt level bit) ....................................................................................................................................38
IL1 (Interrupt level bit) ....................................................................................................................................38
ILR1 (Interrupt level setting register) .............................................................................................................45
ILR2 (Interrupt level setting register) .............................................................................................................45
ILR3 (Interrupt level setting register) .............................................................................................................45
IR (Measurement completion interrupt request flag bit) ..............................................................................164
IX (Index register) ..........................................................................................................................................36
N
N (Negative flag) ............................................................................................................................................38
O
OE (output pin control bit) ............................................................................................................................144
P
P/TX (Operating mode selection bit) ...........................................................................................................144
P0 (Clock selection bit) ................................................................................................................................144
P1 (Clock selection bit) ................................................................................................................................144
PC (Program counter) ...................................................................................................................................36
PCR1 (PWC pulse width control register) ...................................................................................................164
PCR2 (PWC pulse width control register) ...................................................................................................166
PDR0 (Port 0 data register) ...........................................................................................................................92
PDR1 (Port 1 data register) ...........................................................................................................................92
PDR2 (Port 2 data register) ...........................................................................................................................96
PDR3 (Port 3 data register) .........................................................................................................................100
PDR4 (Port 4 data register) .........................................................................................................................106
PDR5 (Port 5 data register) .........................................................................................................................110
PDR6 (Port 6 data register) .........................................................................................................................114
PS (Program status) ......................................................................................................................................36
MB89620 series
IN
315
Register Index