Fujitsu F2MC-8L MB89620 Series Hardware Manual page 21

TABLES
CHAPTER 1 OVERVIEW ....................................................................................................... 1
Table 1.2a MB89620 Series Product Lineup .............................................................................................. 4
Table 1.2b Common Specifications for MB89620 Series ........................................................................... 5
Table 1.3 Package and Corresponding Products ....................................................................................... 6
Table 1.7a Pin Description ........................................................................................................................ 22
Table 1.7b Pin Description for External EPROM Pin (MB89PV620 only) ................................................. 25
Table 1.7c I/O Circuit Type ....................................................................................................................... 26
CHAPTER 3 CPU ................................................................................................................. 31
Table 3.1.1 Vector Table .......................................................................................................................... 34
Table 3.2.1 Interrupt Level ........................................................................................................................ 39
Table 3.4 Interrupt Request and Interrupt Vector ..................................................................................... 44
Table 3.4.1 Interrupt Level Setting Bit and Interrupt Level ....................................................................... 45
Table 3.5 Reset Source ............................................................................................................................ 52
Table 3.5.1 Reset Source and Reset Output (Optional) ........................................................................... 53
Table 3.7 Standby Mode Operating States ............................................................................................... 66
Table 3.7.3 Standby Control Register (STBC) Bits ................................................................................... 71
Table 3.7.5 Pin States in Standby Modes ................................................................................................. 73
Table 3.8.1a Mode Pin Setting ................................................................................................................. 78
Table 3.8.1b Mode Pins and Mode Data .................................................................................................. 79
Table 3.8.2 External Bus Pin Functions in Each Mode ............................................................................. 80
Table 3.8.3 External Bus Pin Control Register (BCTR) Bit ....................................................................... 81
CHAPTER 4 I/O PORTS ....................................................................................................... 87
Table 4.1a Port Function .......................................................................................................................... 89
Table 4.1b Port Register ........................................................................................................................... 89
Table 4.2a Port 0 and 1 Pins .................................................................................................................... 90
Table 4.2b Correspondence between Pin and Register for Port 0 and Port 1 .......................................... 91
Table 4.2.1 Port 0 and 1 Register Function .............................................................................................. 92
Table 4.2.2 Port 0 and 1 Pin State (Single-chip Mode) ............................................................................ 93
Table 4.3a Port 2 Pin ................................................................................................................................ 94
Table 4.3b Correspondence between Pin and Register for Port 2 ........................................................... 95
Table 4.3.1 Port 2 Register Function ........................................................................................................ 96
Table 4.3.2 Port 2 Pin State (Single-chip Mode) ...................................................................................... 97
Table 4.4a Port 3 Pin ................................................................................................................................ 98
Table 4.4b Correspondence between Pin and Register for Port 3 ........................................................... 99
Table 4.4.1 Port 3 Register Function ...................................................................................................... 100
MB89620 series
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