Fujitsu F2MC-8L MB89620 Series Hardware Manual page 222

l Shift clock control circuit
Selects the shift clock from one external and three internal clocks.
If an internal shift clock is selected, the shift clock can be output to the SCK1 (SCK2) pin. If the
external shift clock is selected, the clock input from the SCK1 (SCK2) pin is used as the shift
clock. The SDR register shifts in sync with the shift clock and the shifted-out value is output to
the SO1 (SO2) pin. Similarly, the serial input is obtained by shifting-in the SI1 (SI2) pin input to
the SDR register.
Shift clock counter
l
The shift clock counter counts the number of SDR register shifts generated by the shift clock
and overflows after eight shifts.
The overflow clears the serial I/O transfer start bit in the SMR register (SST = "0") and sets the
interrupt request flag (SIOF = "1"). The shift clock counter stops counting when serial transfer
halts (SST = "0"). The shift clock counter is cleared when serial transfer restarts (SST = "1").
SDR register
l
The SDR register is used to store the transfer data. Data written to this register is converted to
serial and output. Serial input is converted to parallel data and stored in this register.
8-bit serial I/O-1 and 8-bit serial I/O-2 use SDR1 and SDR2 registers respectively.
l SMR register
The SMR register is used to enable or disable serial I/O operation, select the shift clock, set the
transfer (shift) direction, control interrupts, and check the serial I/O status.
8-bit serial I/O-1 and 8-bit serial I/O-2 use SMR1 and SMR2 registers respectively.
MB89620 series
CHAPTER 10 8-BIT SERIAL I/O (SERIAL I/O-1 AND SERIAL I/O-2)
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