Fujitsu F2MC-8L MB89620 Series Hardware Manual page 16

Figure 13.3a Block Diagram of P30/ADST Pin ....................................................................................... 248
Figure 13.3b Block Diagram of P57/AN7 to P50/AN0 Pins .................................................................... 249
Figure 13.3c A/D Converter Registers .................................................................................................... 249
Figure 13.3.1 A/D Control Register 1 (ADC1) ......................................................................................... 250
Figure 13.3.2 A/D Control Register 2 (ADC2) ......................................................................................... 252
Figure 13.3.3 A/D Data Register (ADCD) ............................................................................................... 254
Figure 13.5a A/D Conversion Function (Software Activation) Settings .................................................. 256
Figure 13.5b A/D Conversion Function (Continuous Activation) Settings .............................................. 256
Figure 13.5c Sense Function (Software Activation) Settings .................................................................. 257
Figure 13.5d Sense Function (Continuous Activation) Settings ............................................................. 257
Figure 13.6 Analog Input Equivalent Circuit ........................................................................................... 258
CHAPTER 14 CLOCK MONITOR FUNCTION .................................................................... 263
Figure 14.2 Block Diagram of Clock Monitor Function ........................................................................... 265
Figure 14.3 Block Diagram of P30/ADST/CLKO Pin .............................................................................. 266
Figure 14.4 Clock Output Control Register (CLKE) ................................................................................ 267
APPENDIX ............................................................................................................................ 269
Figure B.1a Direct Addressing ................................................................................................................ 274
Figure B.1b Extended Addressing .......................................................................................................... 274
Figure B.1c Bit Direct Addressing ........................................................................................................... 274
Figure B.1d Index Addressing ................................................................................................................ 275
Figure B.1e Pointer Addressing .............................................................................................................. 275
Figure B.1f General-Purpose Register Addressing ................................................................................ 275
Figure B.1g Immediate Addressing ........................................................................................................ 275
Figure B.1h Vector Addressing ............................................................................................................... 276
Figure B.1i Relative Addressing ............................................................................................................. 276
Figure B.1j Inherent Addressing ............................................................................................................. 276
Figure B.2a JMP @A .............................................................................................................................. 277
Figure B.2b MOVW A, PC ...................................................................................................................... 277
Figure B.2c MULU A............................................................................................................................... 277
Figure B.2d DIVU A ................................................................................................................................ 278
Figure B.2e XCHW A,PC ........................................................................................................................ 278
Figure B.2f Example Using XCHW A,PC ................................................................................................ 278
Figure B.2g Execution Example of CALLV #3 ........................................................................................ 279
Figure Da Memory Map in EPROM Mode (MB89P625) ......................................................................... 289
Figure Db Memory Map in EPROM Mode (MB89P627, MB89P629) ..................................................... 289
Figure Dc Screening Procedure ............................................................................................................. 293
Figure D.2 Memory Map of Piggyback/Evaluation Device ...................................................................... 295
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MB89620 series