Figure 4.4 Block Diagram Of Port 3 Pin; Table 4.4B Correspondence Between Pin And Register For Port 3 - Fujitsu F2MC-8L MB89620 Series Hardware Manual

n Block Diagram of Port 3 Pin
SPL: Pin state specification bit in the standby control register (STBC)
Check: Peripheral inputs continuously are input the pin value. Also, enabling the output enable bit of a
peripheral forcibly sets the pin as a peripheral output, regardless of the DDR3 register value.
n Port 3 Registers
The port 3 registers consist of PDR3 and DDR3.
Each bit in these registers has a one-to-one relationship with a port 3 pin.
Table 4.4b shows the correspondence between pins and registers for port 3.

Table 4.4b Correspondence between Pin and Register for Port 3

Port
Port 3
MB89620 series
PDR (Port data register)
PDR read
PDR read (for bit manipulation instructions)
Output latch
PDR write
DDR
DDR write (Port data direction register)
Stop mode (SPL=1)

Figure 4.4 Block Diagram of Port 3 Pin

Correspondence between register bit and pin
PDR3, DDR3 Bit 7
Corresponding pin P37
From
peripheral
From
To peripheral
peripheral
output
input
output
enable bit
Input
buffer
Output
buffer
Bit 6 Bit 5 Bit 4
P36 P35 P34
CHAPTER 4 I/O PORTS
Pull-up resistor
(optional)
Approx. 50 kΩ /5.0 V
Pin
Bit 3 Bit 2 Bit 1 Bit 0
P33 P32 P31 P30
99