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1.3.3.3
Remote Wake-Up
If a PC supports a reduced power state, it must be possible to bring the system to a fully powered
state in which all management interfaces are available. Typically, the LAN adapter recognizes a
special packet as a signal to wake up the system. This reference design utilizes a Wake on LAN
(WOL) Header to provide standby power to the NIC and the interface for the wake up signal. The
physical connection to the NIC and motherboard is via a WOL Cable provided with the design kit.
See the WOL Header Recommendations document at:
The system BIOS must enable the wake event and provide wake up status. The details of the BIOS
requirements can be obtained from the Intel Corporation web site:
1.3.3.4
Power Management
WfM Baseline compliant systems have four distinct power states: Working, Sleeping, Soft Off, and
Mechanical Off. Soft off is usually provided by a user accessible switch that will send a soft off
request to the system. The PIIX4 provides the power button input for this purpose and
implementation details are described in the schematics. A second optional "override" switch
located in a less obvious place (or removal of the power cord) stops current flow forcing the
platform into the mechanical off state without OS consent. Note that a second "override" switch is
required for legal reasons in some jurisdictions (for example, some European countries). The BIOS
may support the power management requirement either through the APM revision 1.2 or ACPI
revision 1.0 specifications. This reference design's BIOS implementation incorporates both
interfaces. The PIIX4 provides hardware level register support for both the APM and ACPI
specifications. See Intel's web site for additional information:
1.4
Design Recommendations
1.4.1
Voltage Definitions
For the purposes of this document the following nominal voltage definitions are used:
®
Intel
440GX AGPset Design Guide
ftp://download.intel.com/ial/wfm/wol_v14.pdf.
http://developer.intel.com/ial/WfM/design/rwudt/index.htm
http://developer.intel.com/ial/WfM/design/pmdt/index.htm.
Vcc
5.0V
Vcc
3.3V
3.3
Vcc
Voltage is dependent on the five bit VID setting
CORE
Vcc
2.5V
2.5
V
1.5V
TT
V
1.0V
REF
Introduction
1-8
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