Indirect Autoincrement Mode - Texas Instruments MSP430x1xx User Manual

3.3.6

Indirect Autoincrement Mode

The indirect autoincrement mode is described in Table 3−9.
Table 3−9. Indirect Autoincrement Mode Description
Length:
Operation:
Comment:
Example:
Before:
0FF18h
0FF16h
0FF14h
0FF12h
0FA34h
0FA32h
0FA30h
010AAh
010A8h
010A6h
The autoincrementing of the register contents occurs after the operand is
fetched. This is shown in Figure 3−8.
Figure 3−8. Operand Fetch Operation
Assembler Code
MOV @R10+,0(R11)
One or two words
Move the contents of the source address (contents of R10) to
the destination address (contents of R11). Register R10 is
incremented by 1 for a byte operation, or 2 for a word
operation after the fetch; it points to the next address without
any overhead. This is useful for table processing.
Valid only for source operand. The substitute for destination
operand is 0(Rd) plus second instruction INCD Rd.
MOV @R10+,0(R11)
Address Register
Space
0xxxxh
00000h R10 0FA32h
R11 010A8h
04ABBh
PC
0xxxxh
0xxxxh
05BC1h
0xxxxh
0xxxxh
01234h
0xxxxh
Instruction Address
Addressing Modes
Content of ROM
MOV @R10+,0(R11)
After:
Address
Space
0xxxxh PC
0FF18h
0FF16h 00000h R10
R11
0FF14h 04ABBh
0FF12h 0xxxxh
0FA34h 0xxxxh
0FA32h 05BC1h
0xxxxh
0FA30h
010AAh 0xxxxh
010A8h 05BC1h
0xxxxh
010A6h
Operand
+1/ +2
RISC 16-Bit CPU
Register
0FA34h
010A8h
3-15