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IFG1, Interrupt Flag Register 1
7
6
UTXIFG0 †
URXIFG0 †
rw−1
rw−0
†
UTXIFG0
Bit 7
USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty.
0
1
†
URXIFG0
Bit 6
USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received
a complete character.
0
1
Bits
These bits may be used by other modules. See device-specific datasheet.
5-0
† Does not apply to MSP430x12xx devices. See IFG2 for the MSP430x12xx USART0 interrupt flag bits
IFG2, Interrupt Flag Register 2
7
6
Bits
These bits may be used by other modules. See device-specific datasheet.
7-6
UTXIFG1
Bit 5
USART1 transmit interrupt flag. UTXIFG1 is set when U1TXBUF empty.
0
1
URXIFG1
Bit 4
USART1 receive interrupt flag. URXIFG1 is set when U1RXBUF has received
a complete character.
0
1
Bits
These bits may be used by other modules. See device-specific datasheet.
3-2
5
4
No interrupt pending
Interrupt pending
No interrupt pending
Interrupt pending
5
4
UTXIFG1
URXIFG1
rw−1
rw−0
No interrupt pending
Interrupt pending
No interrupt pending
Interrupt pending
USART Peripheral Interface, UART Mode
USART Registers: UART Mode
3
2
1
3
2
1
UTXIFG0 ‡
rw−1
0
0
URXIFG0 ‡
rw−0
13-29
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