Table of Contents
Advertisement
ADC10DTC1, Data Transfer Control Register 1
7
6
rw−(0)
rw−(0)
DTC
Bits
DTC transfers. These bits define the number of transfers in each block.
Transfers
7-0
0
01h-0FFh Number of transfers per block
ADC10SA, Start Address Register for Data Transfer
15
14
rw−(0)
rw−(0)
7
6
rw−(0)
rw−(0)
ADC10SAx
Bits
ADC10 start address. These bits are the start address for the DTC. A write
15-1
to register ADC10SA is required to initiate DTC transfers.
Unused
Bit 0
Unused, Read only. Always read as 0.
5
4
DTC Transfers
rw−(0)
rw−(0)
rw−(0)
DTC is disabled
13
12
11
ADC10SAx
rw−(0)
rw−(0)
rw−(0)
5
4
ADC10SAx
rw−(0)
rw−(0)
rw−(0)
3
2
1
rw−(0)
rw−(0)
10
9
rw−(0)
rw−(1)
3
2
1
rw−(0)
rw−(0)
ADC10 Registers
0
rw−(0)
8
rw−(0)
0
0
r0
ADC10
18-31
Advertisement
Table of Contents
