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2
I
C Module Operation
Figure 15−9. Master Receiver Mode
IDLE
I2CSTT=1
4 x I2CPSC
Generate START
8 x I2CPSC
I2CBB Is Set
I2CSTT Is Cleared
8 x SCL
XA = 0
8 x SCL
4 x I2CPSC
8 x SCL
8 x SCL
Send Slave
Address Bits 6−0
with R/W = 1
Ack
1
No Ack
8 x SCL
Receive Data
Low Byte
1 x SCL
Generate Ack
No
For Low Byte
8 x SCL
Receive Data
High Byte
I2CWORD=0
1 x SCL
Generate Ack
For High Byte
New START?
15-10
USART Peripheral Interface, I
2
Yes
XA = 1
Send Slave Address
Bits 9−8 Extended
With R/W = 0
Send Slave Address
Bits 7−0
Generate 2nd START
Send Slave Address
Bits 9−8 Extended
With R/W = 1
Ack
I2CNDAT
Number Of Bytes
Received?
3
No
No
STOP State?
Or
3
New START?
Yes
2
Yes
2
C Mode
New START?
1
No Ack
NACKIFG Is Set
IDLE
I2CBUSY Is Cleared
No
I2CRM=0
Repeat Mode?
I2CRM=1
STOP State?
Yes
Yes, I2CSTP=1
10 x I2CPSC
Generate STOP
No
8 x I2CPSC
I2CBB Is Cleared
8 x I2CPSC
I2CSTP, I2CMST
Are Cleared
I2CBUSY Is Cleared
No
3
IDLE
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