Texas Instruments MSP430x1xx User Manual page 237

Figure 12−1. Timer_B Block Diagram
TBSSELx
TBCLK 00
ACLK 01
SMCLK 10
11
TBCLGRPx
Group
Load Logic
CCISx
CCI6A 00
Capture
Mode
CCI6B 01
GND 10
Timer Clock
VCC 11
CCI
VCC
TBR=0
EQU0
UP/DOWN
EQU0
Timer Clock
IDx
15
16−bit Timer
Divider
1/2/4/8
Clear
TBCLR
CMx
logic COV
SCS
0
Sync 1
CLLDx
Group
Load Logic
00
01
CCR5
10
CCR4
11
CCR1
OUT
Output
Unit6
Timer Clock
OUTMODx
MCx
0
Count
RC
TBR
Mode
8 10 12 16
CNTLx
00
01
10
11
15
TBCCR6
Load
Compare Latch TBCL6
Compararator 6
EQU6
CAP
0
1
D Set Q
Reset
POR
Timer_B Introduction
Timer Block
EQU0
Set TBIFG
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
0
Set TBCCR6
CCIFG
OUT6 Signal
Timer_B 12-3